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Question about instruction scheduling and dependencies between instructions in 2 different basic blocks
- From: Dave Hudson <gcc at blueteddy dot net>
- To: gcc at gcc dot gnu dot org
- Date: Thu, 07 Jan 2010 09:07:10 +0000
- Subject: Question about instruction scheduling and dependencies between instructions in 2 different basic blocks
I've been working on instruction scheduling issues for our (Ubicom) ISA
and have run into a problem I can't seem to resolve.
The pipeline has a major hazard associated with the generation of
addresses that are loaded from memory - the hazard window is 4
instructions. This is more than enough time for a load of the address,
compare with zero, branch-and-fallthrough and attempted use of the
address but this particular sequence crosses a basic block boundary.
Does anyone have any suggestions about how I might deal with this?
FWIW within a basic block the instruction scheduling is working very
nicely.
Thanks,
Dave