This is the mail archive of the gcc@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: Extending constraints using register subclasses


> From: Andrew Pinski <pinskia@gmail.com>

> To: Jamie Prescott <jpresss@yahoo.com>
> Cc: gcc@gcc.gnu.org
> Sent: Monday, May 11, 2009 4:47:57 PM
> Subject: Re: Extending constraints using register subclasses
> 
> On Mon, May 11, 2009 at 4:45 PM, Jamie Prescott wrote:
> >
> > Hi!
> > I wanted to add finer (one per) register subclasses, so that I can more finely 
> control
> > the register placement inside the inline assembly.
> 
> You don't need that.
> You can just use asm("registername") on variables.
> like so:
> 
> int f(int a)
> {
>   register int r0 __asm__("r0");
>   asm("use %0": "+r"(r0) );
> }

Now I managed to have the approach based on register subclasses working. The above
works too, but I somehow found it less clear and more "global" than inline assembly
constraints.
One thing that I cannot see how to implement clearly with the approach above, is when
you have an instruction (like I use inside the VM with SWI - software interrupts), where
the C type of a register changes between input and output.
For some of them the r0 in input can be a 'char*', and an 'int' (error code) on output.
With inline assembly this can be done pretty cleanly, while I am not aware of how to
do it with the approach above. For clean, I mean cast-less.


- Jamie


      


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]