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Generate Codes for a something like stack/dataflow computer

We are retargetting GCC to a VLIW chip, which runs as a coprocessor to a
general purpose processor. The coprocessor is responsible for
expediating some code sections which have good parallel characteristics
without any dependences. Its ISA enables it can only fetch data
sequentially rather than random access from a on-chip memory which is
shared by the host processor, through dedicated function units named
DBx. The host processor is responsible to place data there, and told the
DBx base address and data length. Once the data is fetched by the
coprocessor, it is stored to local registers owned by the coprocessor,
and before the computing ends, the data will always reside in the
coprocessor's registers. Namely, without spills and it permits no
spills. From the coprocessor standpoint, the instructions supports no
memory operands and no any addressing mode. It supports only register
move and arithmetical operations. It looks something like data flow
computer or stack computer. Let's take the following codes as an example:

int main()
int a[16], b[16], c[16];

compute(a, b, c);
return 0;
void compute(int a[], int b[], int c[])
for (int j = 0; j < 16; j++)
c[j] = a[j] + b[j];

We want to put the function compute() executed on the coprocessor, and
host processor organizes and places the data at proper positions in the
on-chip memory, prepare the DBx function units. Assume DB0 is allocated
to array a[], DB1 to b[], DB2 to c[]. Then the assemble codes for the
coprocessor we want to generate like as follows,

if (data in DB0 not exausted)
goto L1;
goto L2;
get R0, DB0; // load a data from the on-chip memory through DB0 to R0
get R1, DB1;
add R2, R0, R1;
put R2, DB2; // store result to DB2
goto L3;

Could anyone give some hints how to implement that, currently the GCC
internals for addressing mode in the machine description could support that?


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