This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: MIPS atomic memory operations (A.K.A PR 33479).
- From: Daniel Jacobowitz <dan at debian dot org>
- To: David Daney <ddaney at avtrex dot com>
- Cc: Richard Sandiford <rsandifo at nildram dot co dot uk>, GCC Mailing List <gcc at gcc dot gnu dot org>, linux-mips at linux-mips dot org
- Date: Tue, 18 Sep 2007 22:32:35 -0400
- Subject: Re: MIPS atomic memory operations (A.K.A PR 33479).
- References: <46F06980.4080500@avtrex.com>
On Tue, Sep 18, 2007 at 05:12:48PM -0700, David Daney wrote:
> I guess my basic question is: Should MIPS_COMPARE_AND_SWAP have a 'sync' after
> the 'sc'? I would have thought that 'sc' made the write visible to all CPUs,
> but on the SB1 it appears not to be the case.
Yes, a barrier of some sort is definitely necessary. I believe the
SB1 is weakly ordered, and the architecture spec permits both strong
and weak ordering; but it's been a while since I tried this.
--
Daniel Jacobowitz
CodeSourcery