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Re: Modifying ARM code generator for elimination of 8bit writes - need help
> > Tightening the predicates isn't sufficient (and may not even be
> > neccessary). You need to set the constraints so that the compiler
> > knows *how* to fix invalid instructions.
>
> And if I have 4 different constraints in a single insn, and only one of
> them is needing a temporary register, how do I model this?
> This may be the biggest problem. And because byte writes are so common,
> it deserves a good implementation. I can't waste a temporary register
> for each load/store.
You use "X" constraints on the scratch for the other alternatives.
Not that this means your "*arm_movqi" pattern now has three operands, so
doesn't mathc the named "movqi" pattern. You'll probably have to make the
movqi expander allocate a pseudo for the scratch, and also implement
reload_inq/reload_outqi for the cases where no new pseudos are allowed. As I
mentioned before the Alpha backend is probably a good reference for these.
Paul