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Re: Modifying ARM code generator for elimination of 8bit writes - need help


Paul,

On Sunday 04 June 2006 17:57, Paul Brook wrote:
> Because then you have several different patterns for the same
> operation. The different variants of movsi should be part of the same
> pattern so that the compiler can change its mind which variant it
> wants to use.

Together with the comments of Rask Ingemann (Thanks, Rask!), I 
understand now what you mean.

But regarding the fact that swpb() needs a temporary register - or 
alternative - clobber the input register - how can I model this 
behaviour in a single insn? 

> You're confusing constraints and predicates. general_operand is the
> predicate. The predicate says under which conditions the insn will
> match. The constraints tell regalooc/reload how to make sure the
> operands of the instruction are valid.

Yes, my wording was incorrect. But I know already the difference from 
the manual.

> Tightening the predicates isn't sufficient (and may not even be
> neccessary). You need to set the constraints so that the compiler
> knows *how* to fix invalid instructions.

And if I have 4 different constraints in a single insn, and only one of 
them is needing a temporary register, how do I model this?
This may be the biggest problem. And because byte writes are so common, 
it deserves a good implementation. I can't waste a temporary register 
for each load/store.

> The compilcation is that while constraints give sufficient
> information for the compiler to generate correct code they don't help
> generating good code. There are often non-obvious target specific
> ways of reloading invalid addresses. So reload has additional hooks
> (eg. GO_IF_LEGITIMATE_ADDRESS) to provice clever ways of fixing
> invalid operands.

I will look into this region of code to understand what's going on 
there.

Thanks, Paul.

regards

Wolfgang
-- 
We're back to the times when men were men 
and wrote their own device drivers.

(Linus Torvalds)


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