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Re: Scheduler questions (related to PR17808)
On Thursday 30 June 2005 16:18, Andrey Belevantsev wrote:
> Vladimir Makarov wrote:
> > I'll look at this PR today.
>
> We've looked today at this issue. We think the problem is that proposed
> patch of sched_get_condition() treats conditional jumps likely to
> COND_EXECs, but it doesn't fix other places in sched-deps, where
> COND_EXECs are considered. Maxim Kuvyrkov proposed the attached patch,
> which allows gcc to bootstrap on ia64 and fixes the testcase in PR.
Yeah, it fixes the test case and still allows the motion of the
cond_exec insns past the branch. It probably doesn't fix Richard
Earnshaw's problem (which is IMHO a separate problem), but at
least for this case the patch appears to do the right thing.
Of course I can't approve it. But I diffed the output of the
patched compiler against the unpatched one. Looks OK. It is
interesting to see that the "(p6)" checks are in front of those
insns, when in fact we already know that p6 must be true if the
branch is taken (because in gcc, p7 not set implies p6 set ;-).
Are predicate checks free, or should there be some post-pass to
clean up this kind of useless predication?
Thanks for looking at this bug.
Gr.
Steven
.proc bar# .proc bar#
bar: bar:
.prologue .prologue
.body .body
.mmi .mmi
addl r18 = @ltoffx(b#), r1 addl r18 = @ltoffx(b#), r1
;; ;;
ld8.mov r18 = [r18], b# ld8.mov r18 = [r18], b#
nop 0 nop 0
;; ;;
.mmi | .mii
ld4 r15 = [r18] ld4 r15 = [r18]
> nop 0
;; ;;
cmp4.ne p6, p7 = 0, r15 cmp4.ne p6, p7 = 0, r15
> .mmb
nop 0 nop 0
> nop 0
> (p7) br.cond.dpnt .L4
;; ;;
.mmi .mmi
> (p6) mov r16 = r0
(p6) mov r14 = r32 (p6) mov r14 = r32
(p6) mov r17 = r0 (p6) mov r17 = r0
(p6) mov r16 = r0 <
.mib <
nop 0 <
nop 0 <
(p7) br.cond.dpnt .L4 <
;; ;;
.mmi .mmi
adds r16 = 1, r16 adds r16 = 1, r16
st4 [r14] = r17 st4 [r14] = r17
mov r17 = r0 mov r17 = r0
;; ;;
.mmi .mmi
addp4 r14 = r16, r0 addp4 r14 = r16, r0
ld4 r15 = [r18] ld4 r15 = [r18]
cmp4.ne p8, p9 = 0, r16 cmp4.ne p8, p9 = 0, r16
;; ;;
.mib .mib
shladd r14 = r14, 2, r32 shladd r14 = r14, 2, r32
cmp4.gtu p10, p11 = r15, r16 cmp4.gtu p10, p11 = r15, r16
(p11) br.cond.dpnt .L4 (p11) br.cond.dpnt .L4
;; ;;
.L6: .L6:
.pred.rel.mutex p8, p9 .pred.rel.mutex p8, p9
[.L7:] [.L7:]
.mmi .mmi
(p8) ld4 r17 = [r14] (p8) ld4 r17 = [r14]
nop 0 nop 0
adds r16 = 1, r16 adds r16 = 1, r16
;; ;;
.mmi .mmi
st4 [r14] = r17 st4 [r14] = r17
addp4 r14 = r16, r0 addp4 r14 = r16, r0
mov r17 = r0 mov r17 = r0
.mmi .mmi
cmp4.ne p8, p9 = 0, r16 cmp4.ne p8, p9 = 0, r16
ld4 r15 = [r18] ld4 r15 = [r18]
nop 0 nop 0
;; ;;
.mib .mib
shladd r14 = r14, 2, r32 shladd r14 = r14, 2, r32
cmp4.gtu p10, p11 = r15, r16 cmp4.gtu p10, p11 = r15, r16
(p10) br.cond.dptk .L6 (p10) br.cond.dptk .L6
.L4: .L4:
.mii .mii
nop 0 nop 0
addp4 r3 = r15, r0 addp4 r3 = r15, r0
;; ;;
shladd r2 = r3, 2, r32 shladd r2 = r3, 2, r32
;; ;;
.mib .mib
ld4 r8 = [r2] ld4 r8 = [r2]
nop 0 nop 0
br.ret.sptk.many b0 br.ret.sptk.many b0
.endp bar# .endp bar#