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Re: Why the V4QImode vector operations are expanded into many SImode at "oplower" pass?

From: "Ling-hua Tseng" <uranus at it dot muds dot net>
To: Ian Lance Taylor <ian at airs dot com>
Cc: gcc at gcc dot gnu dot org
Date: Thu, 19 May 2005 01:07:59 +0800
Subject: Re: Why the V4QImode vector operations are expanded into many SImode at "oplower" pass?
References: <000301c55bbb$c896dfb0$0201a8c0@uranus> <d6fmnv$37j$1@sea.gmane.org> <20050518153652.M44026@it.muds.net> <m33bskwk44.fsf@gossamer.airs.com>

On 18 May 2005 12:54:03 -0400, Ian Lance Taylor wrote
> "Ling-hua Tseng" <uranus@it.muds.net> writes:
> 
> > I have tried to adjust the constraints to 'r' (general registers) for 
> > the "movv4qi" and "addv4qi" insn patterns,
> > but I got the same problem.
> 
> What about HARD_REGNO_MODE_OK?
> 
> Ian
If the register number is less than FIRST_PSEUDO_REGISTER,
it will always return 1.

References:
- Why the V4QImode vector operations are expanded into many SImode at "oplower" pass?
  - From: Ling-hua Tseng
- Re: Why the V4QImode vector operations are expanded into many SImodeat "oplower" pass?
  - From: Paolo Bonzini
- Re: Why the V4QImode vector operations are expanded into many SImode at "oplower" pass?
  - From: Ling-hua Tseng
- Re: Why the V4QImode vector operations are expanded into many SImode at "oplower" pass?
  - From: Ian Lance Taylor

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