PR target/16482: first scheduling pass on SH4

[<tm_gccmail at kloo dot net>]

Sorry, deleted the original message to which I should be replying, which
screws up the threading, but anyway:

Original message: http://gcc.gnu.org/ml/gcc/2004-10/msg00176.html

Kaz Kojima wrote:

> Thus the first insn scheduling permutes [r4+r161]=r164 into a lifetime
> of R0 and the spill process needs R0 for the expression for [r4+r161]
> because SH-4 uses R0 as the base register for the addressing mode with
> an index register.
>
> Does the first insn scheduling for SH-4 take account of such insn which
> uses R0 implicitly?  Or is it a problem of the reload pass?

The first instruction scheduling pass cannot extend the lifetime of
pseudos which need r0 since there is only one r0 register.

So yes, this sounds like an SH first instruction scheduling pass bug.

Incidentally, I can reproduce the same problem with a small array index
and -fPIC. Compile this with -O2 -mf -fPIC:

int glob1;

adrreg01limm1_set (float *p0)
{
        p0[10] = (float) glob1;
}

test2.c: In function 'adrreg01limm1_set':
test2.c:7: error: unable to find a register to spill in class 'R0_REGS'
test2.c:7: error: this is the insn:
(insn 49 50 18 0 (set (reg/f:SI 1 r1 [162])
        (mem/u:SI (plus:SI (reg:SI 12 r12)
                (reg/f:SI 1 r1 [163])) [0 S4 A32])) 129 {movsi_ie} (nil)
    (expr_list:REG_DEAD (reg/f:SI 1 r1 [163])
        (expr_list:REG_EQUIV (symbol_ref:SI ("glob1") <var_decl 0x401c215c
glob1>)
            (nil))))
test2.c:7: internal compiler error: in spill_failure, at /reload1.c:1881

Toshi