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PR target/16482: first scheduling pass on SH4


Hi,

PR target/16482 is a regression for sh-elf from 3.4.  The following
part of gcc.c-torture/unsorted/SFset.c:

int glob1;
 
adrreg0limm1_set (float *p0)
{
  p0[10000000] = (float) glob1;
}

causes a spill failure for sh-elf on mainline with -m4 -O2.
It seems that the first insn scheduling which has been enabled for
SH-4 on mainline badly interacts with reloading.  The .sched file
for the problematic function looks like:

;;   ======================================================
;;   -- basic block 1 from 15 to 35 -- before reload
;;   ======================================================

;;	  0--> 36   r1=`__fpscr_values'                :(issue+load_store),nothing,memory
;;	  0--> 25   clobber r0                         :nothing
;;	  0--> 26   clobber r158                       :nothing
;;	  0--> 24   r0=r158                            :issue
;;	  1--> 17   r163=`glob1'                       :(issue+load_store),nothing,memory
;;	  1--> 27   use r0                             :nothing
;;	  2--> 37   =[r1]                              :d_lock,nothing,(F1+memory),F1*2
;;	  3--> 18   r165=[r163]                        :(issue+load_store),nothing,memory
;;	  4--> 15   r161=0x2625a00                     :(issue+load_store),nothing,memory
;;	  5--> 33   r1=`__fpscr_values'                :(issue+load_store),nothing,memory
;;	  6--> 19   {r164=flt(r165);use ;}             :issue,F01,F2
;;	  7--> 34   r166=r1+0x4                        :issue,int
;;	  8--> 20   {[r4+r161]=r164;use ;clobber scratc:(issue+load_store),nothing,memory
;;	  9--> 35   =[r166]                            :d_lock,nothing,(F1+memory),F1*2
;;	Ready list (final):  
;;   total time = 9
;;   new head = 16
;;   new tail = 35

Thus the first insn scheduling permutes [r4+r161]=r164 into a lifetime
of R0 and the spill process needs R0 for the expression for [r4+r161]
because SH-4 uses R0 as the base register for the addressing mode with
an index register.

Does the first insn scheduling for SH-4 take account of such insn which
uses R0 implicitly?  Or is it a problem of the reload pass?

I've tried to inhibit the permutation like above for the basic blocks
which have insns with [rN+rM] and R0 liftimes.  It works for me, but
what is the right thing to do?

Regards,
	kaz


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