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Re: GCC DFA Instruction Scheduler
- From: Nathan Sidwell <nathan at codesourcery dot com>
- To: Sonawane Sachin Vijayku <sachinvs at cse dot iitb dot ac dot in>
- Cc: vmakarov at redhat dot com, gcc at gcc dot gnu dot org, gcc at gnu dot org
- Date: Fri, 01 Oct 2004 10:11:01 +0100
- Subject: Re: GCC DFA Instruction Scheduler
- Organization: Codesourcery LLC
- References: <Pine.LNX.4.61.0410011326300.11647@mars.cse.iitb.ac.in>
Sonawane Sachin Vijayku wrote:
Hi all,
I am doing my M.Tech from IIT Bombay and some part of my Project is
related with GCC DFA based Instruction Scheduler.
I am desparately look for an implementation of this DFA based
Instruction Scheduler in GCC, which has been suggested by a paper titled
as "The finite state automaton based pipeline hazard recognizer and
instruction scheduler in GCC" by Vladimir N. Markarov.
Please let me know, which version of GCC has used this new model of
describing pipeline characteristics of which processors through .md file.
and also "First cycle multipass Instruction Scheduling" suggested in the
same paper has been implemented or not.
genautomata.c. Grep the .md files for define_automaton to see which cpus
support it.
I can't recall when it went in, some time in 2000? The gcc release notes
of the version that first contained it will mention it.
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery LLC
nathan@codesourcery.com :: http://www.planetfall.pwp.blueyonder.co.uk