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Re: locking problem with mips atomicity
Richard Henderson wrote:
>
> On Tue, Mar 16, 2004 at 02:44:15PM -0800, Michael Eager wrote:
> > Well, that's surprising. I was able to get rid of all of the
> > other changes.
>
> Not ok. It's not *required* that the compiler reduce all of the
> addresses for you. In particular, this is more likely to fail
> without optimization.
>
> > - : "m" (*__mem), "r"(__val));
> > + : "m" (*__mem), "r"(__val), "r"(__mem));
>
> In addition to just adding the new argument, you have to actually
> use it in the assembly.
Here's yet one more version of the patch.
--
Michael Eager eager@mvista.com 408-328-8426
MontaVista Software, Inc. 1237 E. Arques Ave., Sunnyvale, CA 94085
2004-03-16 Michael Eager <eager@mvista.com>
* libstdc++-v3/config/cpu/mips/atomicity.h: Prevent reg
loads between LL and SC instructions.
Index: ./libstdc++-v3/config/cpu/mips/atomicity.h
===================================================================
RCS file: /cvs/gcc/gcc/libstdc++-v3/config/cpu/mips/atomicity.h,v
retrieving revision 1.9
diff -u -r1.9 atomicity.h
--- ./libstdc++-v3/config/cpu/mips/atomicity.h 27 Feb 2004 00:49:48 -0000 1.9
+++ ./libstdc++-v3/config/cpu/mips/atomicity.h 17 Mar 2004 00:17:48 -0000
@@ -44,14 +44,14 @@
#if _MIPS_SIM == _ABIO32
".set mips2\n\t"
#endif
- "ll %0,%3\n\t"
+ "ll %0,0(%5)\n\t"
"addu %1,%4,%0\n\t"
- "sc %1,%2\n\t"
+ "sc %1,0(%5)\n\t"
".set pop\n\t"
"beqz %1,1b\n\t"
"/* End exchange & add */"
: "=&r"(__result), "=&r"(__tmp), "=m"(*__mem)
- : "m" (*__mem), "r"(__val));
+ : "m" (*__mem), "r"(__val), "r"(__mem));
return __result;
}
@@ -69,13 +69,13 @@
#if _MIPS_SIM == _ABIO32
".set mips2\n\t"
#endif
- "ll %0,%2\n\t"
+ "ll %0,0(%4)\n\t"
"addu %0,%3,%0\n\t"
- "sc %0,%1\n\t"
+ "sc %0,0(%4)\n\t"
".set pop\n\t"
"beqz %0,1b\n\t"
"/* End atomic add */"
: "=&r"(__result), "=m"(*__mem)
- : "m" (*__mem), "r"(__val));
+ : "m" (*__mem), "r"(__val), "r"(__mem));
}
} // namespace __gnu_cxx