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Re: Help with writing RTL for RISC CPU
- From: Richard Henderson <rth at redhat dot com>
- To: David Addison <addy at quadrics dot com>
- Cc: gcc at gcc dot gnu dot org
- Date: Thu, 4 Mar 2004 15:06:05 -0800
- Subject: Re: Help with writing RTL for RISC CPU
- References: <4047B306.5030107@quadrics.com>
On Thu, Mar 04, 2004 at 10:51:50PM +0000, David Addison wrote:
> srl8,byte %0, %1, %0
[...]
> The srl8,byte instruction shifts the loaded DI register appropriately
> based on the alignment of the address in %1. Here %1 must be a single
> register.
You should probably copy non-BWX alpha, since our "extbl" instruction
probably matches up well with your "srl8,byte".
r~