Help with writing RTL for RISC CPU

[David Addison <addy at quadrics dot com>]

Hi, I'm a bit of a newbie to all this gcc stuff so I hope this is the 
correct place to post my query;

We have a RISC like co-processor that needs a two instruction pair to 
load/store data from memory with types with are smaller than DI in size 
(i.e. QI, HI, SI)

e.g. to load a QI integer we need to generate;

           ld1        [%1], %0
           srl8,byte   %0, %1, %0

Where %1 is the memory location address and %0 is one of our 64*DI 
registers.
The ld1 instruction loads a full DI sized object and will mask the 
address to do so. Here %1 can be (register + register) or (register + 
immediate).
The srl8,byte instruction shifts the loaded DI register appropriately 
based on the alignment of the address in %1. Here %1 must be a single 
register.

I currently have this (incorrect) RTL expression (based on gcc 3.3.3 
sparc.md);

   (define_insn "*movqi_insn"
     [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,m")
       (match_operand:QI 1 "input_operand"   "rI,m,r,J,J"))]
     "(register_operand (operands[0], QImode)
       || reg_or_0_operand (operands[1], QImode))"
     "@
      mov\t%1, %0
      ld1\\t%1, %0
      st1\\t%1, %0
      clr1\\t%1
      clr1\\t%1"
     [(set_attr "type" "*,load,store,store,store")
      (set_attr "length" "1,1,1,1,1")])

How should I go about generating these two instruction sequences correctly ?

Do I need to define a split for these memory operand cases ?
How do I force the memory address into a single register for the byte 
shift ?
Or should I copy another architecture that has multi instruction 
sequences for subword accesses (e.g. non BWX Alpha ?)

Cheers
Addy.