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latency in define_insn_reservation
- From: ml at bitbash dot net
- To: gcc at gcc dot gnu dot org
- Date: Mon, 8 Dec 2003 23:08:18 -0700
- Subject: latency in define_insn_reservation
In the DFA pipeline description, is the latency time equal to the number of cycles between instruction issue and instruction results or is it number of cycles btw instr issue and intruction results + 1 (the instr issue cycle also being counted) ?
If instr I is issued cycle = t and the results are usable in cylce t+1, should the latency in define_insn_reservation be 1 or 0?