This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: Trying to work around a 16-bit x86 weirdness

Hash: SHA1

On Tue, Oct 21, 2003 at 08:53:31AM -0400, DJ Delorie wrote:
> > > Have you looked at my old i86 port?  I don't expect it to work with
> > 
> > Yes, most of the machine description is snarfed from your port.
> Ah, cool.
> > (I did the i86.h and i86.c pretty much from scratch, though, as a sort
> > of learning exercise.  I was surprised to see it attempting to work!)
> I think if I were to revisit that port, I'd do it completely
> differently anyway.  I'd break out AH/AL etc as separate registers,
> and use register pairs for HImode.  That way, QImode operations can
> use the AH etc registers too (if the base reg is HImode, it will only
> use AL).

That sounds smart...  Maybe I can have my cake and eat it; I could
always do it later.  Or I can hope that register allocation becomes
*really* smart by the time myour port shapes up so it can use
non-consecutive registers as pairs.  (Maybe it's done already??)

> > Seeing that I snarfed's contents from yours, it must be your bug!
> > :)
> Hence the "I don't expect it to work with current sources" disclaimer.

Strangely, it *broke* sometime last week.  It *used to* work.  I used to
be able to compile my test program completely, and the only sillyness I
had was moving constants through regs into memory.

If I get desperate I'll start undoing my work and going back to previous
CVS GCC's to find the place where it all goes pear-shaped.

Version: GnuPG v1.0.4 (GNU/Linux)
Comment: For info see


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]