ideas for modeling pipeline with bypass registers?

[Greg McGary <greg at mcgary dot org>]

I'm working on a GCC port to a pipelined machine that has 1 insn
latency between ALU operation and numbered-register writeback
(i.e.,  insn-0: ALU op
        insn-1: ...
        insn-2: ALU op result appears in destination register

In order to make ALU ops available with no latency, there's a special
"bypass" register that can be used before the register-file writeback.
This bypass value is available for only one cycle, after which it is
clobbered by the next ALU op.

Questions:

Are there any other GCC ports to CPUs with a similar architectural
feature?

How might this be modeled in GCC?

One idea is to tell GCC there's no latency for register-file writeback
from the ALU, then teach PRINT_OPERAND() to detect the case where it's
outputting a register operand whose value isn't available yet, and
print the bypass register name instead.  Seems very kludgy.

Another idea, which I like much better, but don't yet know if it's
feasible (please offer your opinions) is to explicitly model the ALU
operation first writing ALU result to the bypass register, then emit a
following insn to copy the bypass reg to the originally named dest
register.  The insn scheduler would make sure these operations are
adequately separated in time.  There would be no assembler code
generated for the copy of bypass register to dest register, because
it's done implicitly by the machine.  A wrinkle is that I'd need two
bypass registers, call them bypass-odd and bypass-even to handle the
interleaving of insns that would otherwise clobber a single bypass
register.  E.g.,

    source code:

        r1 = r2 + r3;
        r4 = r1 + r5;
        r6 = r2 + r4;

    timing analysis:

        insn-0: bypass-even <- r2 + r3;
        insn-1: bypass-odd <- bypass-even + r5;
        insn-2: [ r1 <- bypass-even; bypass-even <- r2 + bypass-odd; ]
        insn-3: r4 <- bypass-odd 
        insn-4: r6 <- bypass-even

Observe that the even-numbered insns can only set and write-back from
the even bypass, and can only read-as-operand the odd bypass,
similarly for odd insns with roles reversed.

Is GCC capable of doing this somewhat naturally?

Comments?  Better ideas?

Greg