This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: GCC for 8051 based architectures

Hi Joe,

Joe Buck wrote:
On Tue, Jul 15, 2003 at 10:35:37AM -0700, Julia Nilsson wrote:

There has been lots of research on techniques for dealing with
irregular processors with limited register sets, multiple memory
banks, and odd addressing modes, and commercial compilers for
DSPs and 8-bit microcontrollers aggressively use such techniques
(for example, offset assignment of local variables so that they
can quickly be accessed through address registers with auto
increment or decrement).  GCC does not implement such techniques
because they are not needed for the 32- and 64-bit CISC and RISC
processors that are its main target.  So, GCC lacks the algorithms
needed to get really good code on such processors (though it
is possible to get correct but slow code).

While it's true that gcc assumes the resources, there's no problem as long as you can emulate them. gcc is the sole compiler for the IP2022 and it has one 8-bit accumulator, one 16-bit non-offsettable address reg and 2 offsettable ones (one used as the stack). The code without some of the more interesting RTL hackery that has been added is not actually that bad (with the extra stuff the code is abou 20% smaller than without it).

FWIW the major wins are in fact are not related to any intrinsic characteristic of gcc, but mainly because there is huge pressure on the offsettable address register that is not used as a stack and reload insists on generating redundant reloads. The other major win is that integer promotion on an 8-bit target is *really* expensive. In both cases a reasonably simple RTL-level optimizer solves the problems.

If I were to start doing a lot of work on this port again I'd probably rewrite it to emulate more address registers - this would almost certainly give dramatic simplifications and better code, but right now the code quality is extremely good.

This solution isn't that far from what's been done with LLVM if memory serves.

Regards, Dave

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]