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Re: sched-ebb.c bug (was Re: [3.3 branch] IA64 bootstrap failure)
On Thu, Jul 10, 2003 at 01:35:03AM +0200, Jakub Jelinek wrote:
>
> When schedule_block is run later on, it depends on what rt_cselib
> has been reused for, sometimes true_dependence will return true, sometimes
> false, which determines what insns are added on INSN_DEPEND list and the
> length of INSN_DEPEND list matters when sorting instructions in ready list
> (if they have the same rank but different INSN_DEPEND list lengths,
> the one with longer INSN_DEPEND list is scheduled first, while if
> they have same length, the one with smaller LUID gets scheduled first).
>
Will this help?
H.J.
---
--- gcc/config/ia64/ia64.md.const 2003-06-11 23:22:54.000000000 -0700
+++ gcc/config/ia64/ia64.md 2003-07-09 18:26:55.000000000 -0700
@@ -1049,22 +1049,6 @@
"fcvt.xf %0 = %1"
[(set_attr "itanium_class" "fcvtfx")])
-;; ??? Suboptimal. This should be split somehow.
-(define_insn "floatdidf2"
- [(set (match_operand:DF 0 "register_operand" "=f")
- (float:DF (match_operand:DI 1 "register_operand" "f")))]
- "!INTEL_EXTENDED_IEEE_FORMAT"
- "fcvt.xf %0 = %1\;;;\;%,fnorm.d %0 = %0"
- [(set_attr "itanium_class" "fcvtfx")])
-
-;; ??? Suboptimal. This should be split somehow.
-(define_insn "floatdisf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float:SF (match_operand:DI 1 "register_operand" "f")))]
- "!INTEL_EXTENDED_IEEE_FORMAT"
- "fcvt.xf %0 = %1\;;;\;%,fnorm.s %0 = %0"
- [(set_attr "itanium_class" "fcvtfx")])
-
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
(fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
@@ -5534,3 +5518,22 @@
"addp4_optimize_ok (operands[1], operands[2])"
"addp4 %0 = %1, %2"
[(set_attr "itanium_class" "ialu")])
+
+;; These 2 patterns have to be last so that we get the same function
+;; name for the same pattern regardless if these patterns are generated
+;; or not.
+;; ??? Suboptimal. This should be split somehow.
+(define_insn "floatdidf2"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (float:DF (match_operand:DI 1 "register_operand" "f")))]
+ "!INTEL_EXTENDED_IEEE_FORMAT"
+ "fcvt.xf %0 = %1\;;;\;%,fnorm.d %0 = %0"
+ [(set_attr "itanium_class" "fcvtfx")])
+
+;; ??? Suboptimal. This should be split somehow.
+(define_insn "floatdisf2"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (float:SF (match_operand:DI 1 "register_operand" "f")))]
+ "!INTEL_EXTENDED_IEEE_FORMAT"
+ "fcvt.xf %0 = %1\;;;\;%,fnorm.s %0 = %0"
+ [(set_attr "itanium_class" "fcvtfx")])