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Re: Pre_dec and Post_inc insns
- From: Hans-Peter Nilsson <hp at bitrange dot com>
- To: tm_gccmail at mail dot kloo dot net
- Cc: Natasha Wilson <nat_w at operamail dot com>, <gcc at gcc dot gnu dot org>
- Date: Wed, 9 Jul 2003 17:09:31 -0400 (EDT)
- Subject: Re: Pre_dec and Post_inc insns
On Wed, 9 Jul 2003 tm_gccmail@mail.kloo.net wrote:
> The load latency usually is two, BTW. This is fairly typical for a
> pipelined processor with 5 stages. The Pentium, the SH, many MIPS and
> other processors have a load latency of two clocks.
But one I'm working on only has a one cycle load latency...
Nevertheless, I hope you get my point that the usefulness of
generating autoincdec before sched1 is a highly target-dependent
detail, and that forcing one way or the other by making
assumptions on universal latency figures would be bad.
brgds, H-P