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Re: Pre_dec and Post_inc insns
- From: <tm_gccmail at mail dot kloo dot net>
- To: Hans-Peter Nilsson <hp at bitrange dot com>
- Cc: Natasha Wilson <nat_w at operamail dot com>, gcc at gcc dot gnu dot org
- Date: Wed, 9 Jul 2003 13:34:53 -0700 (PDT)
- Subject: Re: Pre_dec and Post_inc insns
On Wed, 9 Jul 2003, Hans-Peter Nilsson wrote:
> On Tue, 8 Jul 2003 tm_gccmail@mail.kloo.net wrote:
> > IMHO, the pre/post dec/inc shouldn't be generated before sched1 because
> > these cause major problems with instruction scheduling.
> >
> > Consider a processor with a memory load latency of two clocks:
> >
> > mov.l @r4+,r1
> > mov.l @r4+,r2
> > mov.l @r4+,r3
> > add r2,r3
> >
> > sched1 will be unable to reorder this sequence to:
> >
> > add #4,r4
> > mov.l @r4+,r2
> > mov.l @r4,r3
> > add #-8,r4
> > mov.l @r4,r1
> > add r2,r3
> >
> > because of the post-increment addressing.
>
> But if the load latency is one insn, then reordering would not
> be a certain win, and might instead lose, at least size-wise.
If the load latency is one, then sched1 should not reorder the
instructions as indicated.
The load latency usually is two, BTW. This is fairly typical for a
pipelined processor with 5 stages. The Pentium, the SH, many MIPS and
other processors have a load latency of two clocks.
Toshi