Re: RFC: using clz for comparing to zero on the tree level.

[Andrew Pinski <pinskia at physics dot uc dot edu>]

In the case I mainly was considering was x==0||y==0, where on PPC (and 
mostly likely on ARM) the asm with clz would be shorter and faster,

PPC:
  cntlzw tmp1,x
  cntlzw tmp2,y
  or tmp3,tmp1,temp2
  srwi out, tmp3, 5

PPC (old way):
  subfic tmp1, x, 0
  adde tmp2, tmp1, x
  subfic tmp4, x, 0
  adde tmp3, tmp4, x
  or out, tmp3, tmp1

See that in the way that I am proposing it takes only 4 instructions 
instead of the current 5.
(in arm it will mostly do the same).

I think I have a patch for the rs6000 machine description that changes 
seq to do the expand (I have bootstrapped on ppc-darwin), the only 
problem is that it produces slower code for (i==0)+a ().


Thanks,
Andrew Pinski



On Friday, May 9, 2003, at 10:27 US/Eastern, Richard Earnshaw wrote:

> > On Thu, May 08, 2003 at 12:36:35PM -0400, David Edelsohn wrote:
> > > 	Not Alpha and not ARM V5, which have single instruction clz?
> >
> > PPC:
> > 	cntlz	tmp, in
> > 	srwi	out, tmp, 5
> >
> > Alpha:
> > 	cmpeq	in, 0, out
> >
> > ARM:
> > 	cmp	in, #0
> > 	movne	out, #0
> > 	moveq	out, #1
> >
> > Hmm, so it might be a win for ARM.  You'll have to work out
> > with Richard Earnshaw how you want to arrange these costs.
> > At the moment arm_rtx_costs doesn't tell you that the SEQ
> > operation takes 3 instructions.
>
> for an seq expander the shortest (though not necessarily fastest) 
> sequence
> on ARMv5 would be
>
> 	clz	t1, in
> 	mov	out, t1, lsr #5
>
> But that's probably best left as a back-end expansion of the canonical 
> RTL:
>
> 	(set (out) (eq (in) (const_int 0)))
>
> which can be expanded after reload with a split pattern.
>
> R.