Re: gcc internals question

[Spundun Bhatt <spundun at ISI dot EDU>]

On Thu, 2003-02-13 at 07:45, Ricardo Anguiano wrote:
> See the gcc internals info page titled "Flags in an RTL Expression",
> aka, (gccint) Flags:

Thanx to Ricardo and Dale for pointing me to the page. I cant believe I
searched that same page twice mem/s and not once for just /s. :|

I sort of fixed the previous problem.(Is details are below my this new
problem). But I am having ice on another template I have recently added.
The error is same, unrecognizable insn.But for the next template.
 internal error--unrecognizable insn:
(insn 46 45 47 (set (reg:SI 128)
        (and:SI (not:SI (ashift:SI (const_int 255 [0xff])
                    (minus:SI (const_int 24 [0x18])
                        (ashift:SI (reg:SI 127)
                            (const_int 3 [0x3])))))
            (reg:SI 128))) -1 (insn_list 44 (insn_list 45 (nil)))
    (nil))
Now here I think I dont understand some fundamental stuff. I think I
have got all the templates needed to translate this template to assembly
instructions. And I think thats all you need. (My assumption no.1, I
believe if you have a complex template and all its components are
templatized using other small templates then.. it should work
Here is the list of templates which (I think) are going to be used to
recognize the template above.

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "r")
		  (match_operand:SI 2 "gpc_reg_operand" "r")))]
  ""
  "SUBU %0,%1,%2")

(define_insn ""
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
		(match_operand:SI 2 "and_operand" "?r,K")))]
  ""
  "@
   AND %0,%1,%2
   ANDIC %0,%1,%b2"
  [(set_attr "length" "4")])

(define_insn "ashlsi3_no_power"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
  ""
  "{SL|SLL}%I2 %0,%1,%h2"
  [(set_attr "length" "8")])

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
  ""
  "NOT %0,%1")

All these are present in my md file. My backend is basically derived
from the powerpc backend and this part of code that I am trying to make
work is something I copied from alpha and modified it for my needs. 
So here is the basic analytical problem.
Considering that all the above templates are present in the md file, I
dont understand why gcc should have any difficulty in recognising the
complex template.  Is there any thing else that could go wrong. 
I would really appreciate if anybody has any hints, guesses, pointers
regarding this.
Thanx again for all your help
Spundun

And now the solution that I found about my previous question.
(insn 14 13 15 (set (reg:SI 120)
        (mem/s:SI (and:SI (reg:SI 117)
                (const_int -4 [0xfffffffc])) 0)) -1 (nil)
    (nil))
gcc was not recognizing this template.

I then configured gcc as a cross for alpha and tried to compile the same
code and see what template it was matching for. I saw that it was using
a simple move template... so it seemed that the mov template could take
in the and part as part of the address operand. I assumed that somewhere
in alpha.c they allow and construct to be part of address operand and
they have special assembly instruction (unaligned load) for such cases.
Then I looked at my instruction set and the loads ignore the last 2 bits
of address, so I just removed the and construct and simply put the
unaligned address as the argument. In the assemply code it will be
passed as unaligned address, but the hardware will silently make aligned
memory access.
:)