This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: An unusual Performance approach using Synthetic registers
- From: Michael S. Zick <mszick at goquest dot com>
- To: <tm_gccmail at mail dot kloo dot net>
- Cc: Andy Walker <ja_walker at earthlink dot net>,gcc at gcc dot gnu dot org
- Date: Wed, 8 Jan 2003 13:54:32 -0600
- Subject: Re: An unusual Performance approach using Synthetic registers
- References: <Pine.LNX.4.21.0301081122160.21471-100000@mail.kloo.net>
Toshi,
That is really great detail work!
Could you please do the same for case 2 and 3?
Mike
On Wednesday 08 January 2003 01:39 pm, tm_gccmail@mail.kloo.net wrote:
> We've tried to tell you several times.
>
So I'm listening, go for case 2 and case 3 also, please.
>
> XCHG issues a BUS LOCK on the external bus for the duration of the
> instruction if a memory operand used.
>
> Assuming an 800 Mhz P3, with a 133 Mhz external bus, you first need to:
>
> 1. Synchronize with the external bus
>
> There's a 6:1 differential between the internal clock and the external
> clock, so it can take up to 5 clock cycles to sync the buses.
>
> 2. Get a bus lock
>
> Takes at least one bus clock, or 6 internal clocks
>
> 3. Execute the instruction
>
> Possibly one or two clocks.
>
> 4. Release the bus lock.
>
> Requires resyncing with the external bus again, so up to 5 clocks.
> Takes a bus clock, or 6 internal clocks
>
> So basically, it's at least 18 clocks, and might be as bad as 23 clocks
> to execute XCHG on an 800 Mhz P3.
>