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Re: An unusual Performance approach using Synthetic registers
- From: dewar at gnat dot com (Robert Dewar)
- To: gcc at gcc dot gnu dot org, marcel_cox at hotmail dot com
- Date: Wed, 8 Jan 2003 06:45:01 -0500 (EST)
- Subject: Re: An unusual Performance approach using Synthetic registers
> What you're describing is actually bad on the Pentium, and probably
> subsequent implementations as well.
> The Pentium can dual-issue loads as long as they reference separate cache
> ways. So, manually sorting the stack so contiguous accesses are localized
> increases the probability of the loads accessing the same cache way, thus
> decreasing the probability of single-issuing.
I would guess this would be dominated by the improvement in icache behavior
from the use of shorter offsets.