Re: An unusual Performance approach using Synthetic registers

[<tm_gccmail at mail dot kloo dot net>]

On Tue, 7 Jan 2003, Robert Dewar wrote:

> > First, XCHG is what I think of as an Operating System instruction.  It is 
> > quite valuable because the exchange can be limited to a single process on a 
> > single processor in a multiprocessor system, in conjunction with the locking 
> > process.  It is one of the very reliable ways to implement semaphores.  
> 
> Please look through the instruction set more carefully, this is NOT the way
> you would implement any sychronization instructions on the x86.
> 
> Also, be very careful about timing of instructions when you start to look
> at the complex instructions of the x86. No one should even think of generating
> code for the x86 without reading the Intel guide for compiler writers. 
> Basically the rule on most variants of the x86 is that you should treat
> it as a conventional load/store RISC machine when it comes to generating
> code.

Yes, read-modify-write operations on memory locations is very bad,
especially on in-order execution members of the x86 family (Pentium and
below). The problem is that RMW operations stall the pipeline because the
modify/write cannot be performed until the load completes.

So basically:

1) Load occurs
2) Processor stalls for two clocks waiting for the load to occur
3) Modify is done
4) Write is done

If the code is generated as for a strict load/store architecture, then
other instructions can be executed during the latency of the load
instruction to perform useful instructions.

Toshi