This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: An unusual Performance approach using Synthetic registers
- From: Momchil Velikov <velco at fadata dot bg>
- To: dewar at gnat dot com (Robert Dewar)
- Cc: ja_walker at earthlink dot net, lord at emf dot net, mszick at goquest dot com,gcc at gcc dot gnu dot org
- Date: 07 Jan 2003 14:06:04 +0200
- Subject: Re: An unusual Performance approach using Synthetic registers
- References: <20030107115052.04121F28F4@nile.gnat.com>
>>>>> "Robert" == Robert Dewar <dewar@gnat.com> writes:
>> I am pretty familiar with the x86 instruction set, but I clearly recall that
>> I have never seen anything like this. Is there such a thing in the x86
>> instruction set, and if so, what is it called? Is it perhaps one of the
>> testing instructions?
Robert> There is no prefetch instruction as such on the x86, but of course any
Robert> access acts as a prefetch in practice.
There is, actually,
Opcode Instruction Description
0F 18 /1 PREFETCHT0 m8 Move data from m8 closer to the processor using T0 hint.
0F 18 /2 PREFETCHT1 m8 Move data from m8 closer to the processor using T1 hint.
0F 18 /3 PREFETCHT2 m8 Move data from m8 closer to the processor using T2 hint.
0F 18 /0 PREFETCHNTA m8 Move data from m8 closer to the processor using NTA hint.
Description
Fetches the line of data from memory that contains the byte specified
with the source operand to a location in the cache hierarchy
specified by a locality hint:
* T0 (temporal data) prefetch data into all levels of the cache
hierarchy. Pentium III processor 1st- or 2nd-level cache. Pentium
4 and Intel Xeon processor 2nd-level cache.
* T1 (temporal data with respect to first level cache) prefetch data
into level 2 cache and higher. Pentium III processor 2nd-level
cache. Pentium 4 and Intel Xeon processor 2nd-level cache.
* T2 (temporal data with respect to second level cache) prefetch data
into level 2 cache and higher. Pentium III processor 2nd-level
cache. Pentium 4 and Intel Xeon processor 2nd-level cache.
* NTA (non-temporal data with respect to all cache levels) prefetch
data into non-temporal cache structure and into a location close to
the processor, minimizing cache pollution. Pentium III processor
1st-level cache Pentium 4 and Intel Xeon processor 2nd-level cache
~velco