tic4x assemble enhancements

["Svein E. Seldal" <Svein dot Seldal at solidas dot com>]

Hello,

I have been working extensively on (binutils) tic4x-as lately. I believe 
it is fairly stable - I've reached my level of features that I want. Now 
I just need to test it extensively.

I have made substansial changes to the opcode definition 
(include/opcodes/tic4x.h) -- to make it simpler to do maintenance on it 
in the future. In this file a class concept is used. Each insn is placed 
into a class, based on its argument syntax. Thus the total opcode list 
is far easier to keep complete/free from bugs. If I refer to a class in 
this mail, please see this file.

This is the list of changes that may or may not affect (ti)c4x-gcc:

   - New commandline arguments are added, and some old ones are 
depreciated. Take a look at the bottom for a --help dump.
   - c33 is now supported
   - Gas is now fully ortogonal where it can be. E.g. mpyf r0 || addf 
r0 is legal (equal to mpyf r0,r0,r0 || addf r0,r0,r0). All aliased forms 
of insns are now accepted: mpyf3_addf3, mpyf_addf3, mpyf3_addf, 
mpyf_addf, addf3_mpyf3, addf_mpyf3, addf3_mpyf and addf_mpyf are all 
refering to the same insn!
   - Fixed the bugs in the old c4x-as: Added: addi_mpyi, addi3_mpyi3, 
or_sti, stf_ldf, sti_ash, stf_frieee, stf_toieee. Fixed bug in xor3.
   - Float insn wont accept non-float registers any more
   - The new c32 enhanced opcodes (use the -menhanced switch) are 
implemented. Internally they affect the argument type 'i' and 'j', and 
they allow use of registers where otherwise an indirect addressing 
should be used.
   - ... and a pile of other changes ...

I was hoping that gcc could improve from these changes. I am no skilled 
gcc-programmer, so I was hoping you could make something out of this. I 
can help, if you need it, but as I said, I'm not a skilled gcc 
programmer (yet... ;). Please let me know.

BTW! When I tried to compile gcc (from HEAD) with my configure patch 
installed. It died when it tried to compile _ffsdi2 from libgcc.c. xgcc 
generates a "ldhi xx,rs" opcode. I assumed that this op would only work 
on Rx registers. The c4x manual is a but vague on this - but you have 
proof that it works with non-Rx register, right? Anyway, I have removed 
the Rx contstraint from the op!

PS! What is the state of the c4x configure patch you have approved? It 
still isnt patched :(

Regards,
Svein Seldal
TIC4X Binutils maintainer




Dump from "tic4x-as --help":
----------------------------
TIC4X options:
  -mcpu=CPU  -mCPU        select architecture variant. CPU can be:
                            30 - TMS320C30
                            31 - TMS320C31, TMS320LC31
                            32 - TMS320C32
                            33 - TMS320VC33
                            40 - TMS320C40
                            44 - TMS320C44
  -mrev=REV               set cpu hardware revision (integer numbers).
                          Combinations of -mcpu and -mrev will 
enable/disable
                          the appropriate options (-midle2, -mlowpower and
                          -menhanced) according to the selected type
  -mbig                   select big memory model
  -msmall                 select small memory model (default)
  -mregparm               select register parameters (default)
  -mmemparm               select memory parameters
  -midle2                 enable IDLE2 support
  -mlowpower              enable LOPOWER and MAXSPEED support
  -menhanced              enable enhanced opcode support