This is the mail archive of the
gcc@gcc.gnu.org
mailing list for the GCC project.
Re: state of 3.2.1-pre: how far from release?
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: Michael Matz <matz at suse dot de>
- Cc: Geoff Keating <geoffk at geoffk dot org>, Richard Henderson <rth at redhat dot com>, Daniel Berlin <dan at dberlin dot org>, gcc at gcc dot gnu dot org
- Date: Wed, 06 Nov 2002 10:32:38 -0500
- Subject: Re: state of 3.2.1-pre: how far from release?
>>>>> Michael Matz writes:
Michael> Which rtx do contain the pseudos here? regno is a hard reg, right? So
Michael> does op1 contain pseudos?
A larger fragment of the code generating the parallel is:
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
op1 = replace_equiv_address (operands[1],
force_reg (SImode, XEXP (operands[1], 0)));
for (i = 0; i < count; i++)
XVECEXP (operands[3], 0, i)
= gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
adjust_address (op1, SImode, i * 4));
op1 contains the memref forced into a reg. This produces RTL like:
(insn 1842 11909 11910 (set (reg/f:SI 929)
(plus:SI (reg/f:SI 31 r31)
(const_int 520 [0x208]))) 36 {*addsi3_internal1} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 31 r31)
(const_int 520 [0x208]))
(nil)))
(insn 1856 1853 16458 (parallel[
(set (reg:SI 4 r4)
(mem/s:SI (reg/f:SI 929) [0 S4 A32]))
(set (reg:SI 5 r5)
(mem/s:SI (plus:SI (reg/f:SI 929)
(const_int 4 [0x4])) [0 S4 A32]))
(set (reg:SI 6 r6)
(mem/s:SI (plus:SI (reg/f:SI 929)
(const_int 8 [0x8])) [0 S4 A32]))
(set (reg:SI 7 r7)
(mem/s:SI (plus:SI (reg/f:SI 929)
(const_int 12 [0xc])) [0 S4 A32]))
] ) 322 {*rs6000.md:8746} (insn_list:REG_DEP_OUTPUT 1843 (insn_list:REG_DEP_OUTPUT 1846 (insn_list 1842 (insn_list:REG_DEP_ANTI 1849 (nil)))))
(nil))
eliminate_regs_in_insn() modification of the pseudo in the first
expression does not affect the pseudo in the other expressions.
David