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Re: Status of SSE builtins
> On Tue, 29 Oct 2002, Jan Hubicka wrote:
> > We didn't released compiler with SSE2 support yet. I guess if someone
> > tried them, they didn't work on CVS compiler he will expect them to be
> > fixed in the release.
>
> You mean, SSE2 intrinsics, not general support for SSE2, which already
> was in GCC 3.1, right? Or did I misread gcc-3.1/changes.html?
Yes.
I just noticed that the SSE2 intrinsics are not mentioned, I've added
them as well as few other changes I can come with. I will try to
mention more later.
>
> The compiler now supports MMX, 3DNow!, SSE, and SSE2
> instructions. Options -mmmx, -m3dnow, -msse, and -msse2 will
> enable the respective instruction sets. Intel C++ compatible
> MMX/3DNow!/SSE intrinsics are implemented. SSE2 intrinsics
> will be added in next major release.
>
> > I will add note about SSE1 builtins, as I've fixed number of bugs there.
> > Should this come to 3.2.1 notes, 3.3 notes or both?
>
> As far as I remember your patches, many which were applied both to the 3.2
> branch and mainline (IIRC), I'd say yes.
I am attaching the 3.2 changes. In case you feel it as good idea, I
will apply same changes to 3.3 too.
I am not sure whether people see 3.3 as successor 3.2.1 or whether they
see them independent (as they really are)
Index: gcc-3.2/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-3.2/changes.html,v
retrieving revision 1.33
diff -c -3 -p -r1.33 changes.html
*** gcc-3.2/changes.html 16 Oct 2002 19:26:07 -0000 1.33
--- gcc-3.2/changes.html 29 Oct 2002 20:35:07 -0000
*************** a list of bugs fixed in this release.</p
*** 86,96 ****
--- 86,107 ----
<h2>New Targets and Target Specific Improvements</h2>
+ <h3>IA-32</h3>
+ <ul>
+ <li>Fixed number of bugs in SSE and MMX intrinsics.</li>
+ <li>Fixed common compiler crashes with SSE instruction set enabled
+ (implied by <code>-march=pentium3</code>, <code>pentium4</code>,
+ <code>athlon-xp</code>)</li>
+ <li>__m128 and __m128i is not 128bit aligned when used in structures.
+ </ul>
<h3>x86-64</h3>
<ul>
<li>A bug whereby the compiler could generate bad code for
<code>bzero</code> has been fixed.</li>
+ <li>ABI fixes (implying ABI incompatibilities with previous version in some
+ side cases)</li>
+ <li>Fixed prefetch code generation</li>
</ul>
</body>
Index: gcc-3.3/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-3.3/changes.html,v
retrieving revision 1.11
diff -c -3 -p -r1.11 changes.html
*** gcc-3.3/changes.html 14 Oct 2002 17:12:09 -0000 1.11
--- gcc-3.3/changes.html 29 Oct 2002 20:35:07 -0000
***************
*** 185,191 ****
<li>The HP-PA port now defaults to scheduling for the PA8000 series
of processors. Scheduling support for the PA7300 processor has
been added.</li>
! <li>The SPARC, HP-PA, SH4, and x86 ports have been converted to
use the DFA processor pipeline description.</li>
<li>The following NetBSD configurations for the SuperH processor family
have been added:
--- 185,191 ----
<li>The HP-PA port now defaults to scheduling for the PA8000 series
of processors. Scheduling support for the PA7300 processor has
been added.</li>
! <li>The SPARC, HP-PA, SH4, and partly x86 ports have been converted to
use the DFA processor pipeline description.</li>
<li>The following NetBSD configurations for the SuperH processor family
have been added:
***************
*** 201,206 ****
--- 201,213 ----
<li>SH5, SHmedia, little-endian, 64-bit default,
<code>sh64le-*-netbsd*</code></li>
</ul></li>
+ <li>The following changes have been made to the IA-32/x86-64 port:
+ <ul>
+ <li>SSE2 and 3dNOW! intrinsics are now supported</li>
+ <li>Support for thread local storeage has been added to both IA-32
+ and x86-64 ports.
+ <li>The x86-64 port has been significantly improved</li>
+ </ul>
<li>The following changes have been made to the MIPS port:
<ul>
<li>All configurations now accept the <code>-mabi</code>