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Re: Illegal code generation: gcc-3.2 --target=m68k-elf
- From: Peter Barada <pbarada at mail dot wm dot sps dot mot dot com>
- To: rth at redhat dot com
- Cc: Peter dot Barada at motorola dot com, gcc at gcc dot gnu dot org, Peter dot Barada at motorola dot com
- Date: Tue, 22 Oct 2002 11:29:19 -0400
- Subject: Re: Illegal code generation: gcc-3.2 --target=m68k-elf
- References: <200210212322.g9LNMOX20258@hyper.wm.sps.mot.com> <20021022062737.GD15658@redhat.com>
>> (insn 690 689 691 (set (subreg:SI (reg/v:HI 40) 0)
>> (plus:SI (subreg:SI (reg/v:HI 40) 0)
>> (const_int 1 [0x1]))) 99 {*addsi3_5200} (nil)
>> (nil))
>>
>> Looks like combine put the two instructions together, but there is no
>> instruction in the ColdFire that can allow for this to happen (I guess
>> it found the pattern for addhi3 and assumed that it is valid for
>> ColdFire?).
>
>No. The constraints for addsi3_5200 say it's valid. And indeed
>it would be if R40 were allocated to a register.
Ok, so the add is valid, but this RTL has to be broken up into insns
later since the add can't deal with the subregs, right?
>> (insn 690 1150 691 (set (mem:SI (plus:SI (reg/f:SI 14 %a6)
>> (const_int -428 [0xfffffe54])) [0 rotate S4 A16])
>> (plus:SI (mem:SI (plus:SI (reg/f:SI 14 %a6)
>> (const_int -428 [0xfffffe54])) [0 rotate S4 A16])
>> (reg:SI 0 %d0))) 99 {*addsi3_5200} (nil)
>> (nil))
>>
>> Now the RTL is bogus since the store to memory is *SImode* wide
>> whereas the original variable is HImode.
>
>Are you _sure_ you're showing us everything? There should have
>been some inefficient jiggery-pokery with subreg reloads. This
>should not have been the real stack slot for R40, but somewhere
>else.
I don't see *any* fiddling with subregs. I would have expected to see
a HImode load into a regieter, followed by the SImode add, followed by
an HImode store into the stack slot, but no. I thought I got
everything relavent. Here's *every* references to R40 from
yy.c.20.lreg:
(note 21 20 22 ("yy.c") 554)
(insn 22 21 23 (set (reg/v:HI 40)
(const_int 0 [0x0])) 33 {*m68k.md:1024} (nil)
(nil))
...
(note 522 521 523 ("yy.c") 622)
(insn 523 522 524 (set (reg/v:HI 40)
(const_int 0 [0x0])) 33 {*m68k.md:1024} (nil)
(nil))
...
(insn 677 676 678 (set (reg:SI 182)
(and:SI (subreg:SI (reg/v:HI 40) 0)
(const_int 3 [0x3]))) 177 {andsi3_5200} (nil)
(nil))
...
(note 688 687 689 ("yy.c") 640)
(note 689 688 690 NOTE_INSN_DELETED)
(insn 690 689 691 (set (subreg:SI (reg/v:HI 40) 0)
(plus:SI (subreg:SI (reg/v:HI 40) 0)
(const_int 1 [0x1]))) 99 {*addsi3_5200} (nil)
(nil))
R40's name is 'rotate', and here's *every* referneces to 'rotate' or
R40 from yy.c.21.greg(including context):
Reloads for insn # 22
Reload 0: reload_out (HI) = (reg/v:HI 40)
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
reload_out_reg: (reg/v:HI 40)
reload_reg_rtx: (reg:HI 0 %d0)
...
Reloads for insn # 523
Reload 0: reload_out (HI) = (reg/v:HI 40)
DATA_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
reload_out_reg: (reg/v:HI 40)
reload_reg_rtx: (reg:HI 0 %d0)
...
Reloads for insn # 677
Reload 0: reload_in (SI) = (const_int 3 [0x3])
reload_out (SI) = (reg:SI 0 %d0 [182])
DATA_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (const_int 3 [0x3])
reload_out_reg: (reg:SI 0 %d0 [182])
reload_reg_rtx: (reg:SI 0 %d0 [182])
Reload 1: reload_in (HI) = (reg/v:HI 40)
DATA_REGS, RELOAD_FOR_INPUT (opnum = 2), optional
reload_in_reg: (reg/v:HI 40)
...
Reloads for insn # 690
Reload 0: reload_in (SI) = (const_int 1 [0x1])
DATA_REGS, RELOAD_FOR_INPUT (opnum = 2)
reload_in_reg: (const_int 1 [0x1])
reload_reg_rtx: (reg:SI 0 %d0)
...
(note 21 20 22 ("yy.c") 554)
(insn 22 21 1023 (set (reg:HI 0 %d0)
(const_int 0 [0x0])) 33 {*m68k.md:1024} (nil)
(nil))
(insn 1023 22 23 (set (mem:HI (plus:SI (reg/f:SI 14 %a6)
(const_int -428 [0xfffffe54])) [0 rotate S2 A16])
(reg:HI 0 %d0)) 33 {*m68k.md:1024} (nil)
(nil))
...
(note 522 521 523 ("yy.c") 622)
(insn 523 522 1114 (set (reg:HI 0 %d0)
(const_int 0 [0x0])) 33 {*m68k.md:1024} (nil)
(nil))
(insn 1114 523 524 (set (mem:HI (plus:SI (reg/f:SI 14 %a6)
(const_int -428 [0xfffffe54])) [0 rotate S2 A16])
(reg:HI 0 %d0)) 33 {*m68k.md:1024} (nil)
(nil))
...
(note 674 671 939 ("yy.c") 639)
;; Start of basic block 32, registers live: 10 [%a2] 14 [%a6] 15 [%sp] 33 34 35 37 38 39 40 41 43 46 62
(note 939 674 675 [bb 32] NOTE_INSN_BASIC_BLOCK)
(note 675 939 676 NOTE_INSN_DELETED)
(note 676 675 1142 NOTE_INSN_DELETED)
(insn 1142 676 677 (set (reg:SI 0 %d0 [182])
(const_int 3 [0x3])) 30 {*m68k.md:993} (nil)
(nil))
(insn 677 1142 678 (set (reg:SI 0 %d0 [182])
(and:SI (reg:SI 0 %d0 [182])
(mem:SI (plus:SI (reg/f:SI 14 %a6)
(const_int -428 [0xfffffe54])) [0 rotate S4 A16]))) 177 {andsi3_5200} (nil)
(nil))
(insn 678 677 679 (set (reg/f:SI 8 %a0 [183])
(plus:SI (reg/f:SI 14 %a6)
(reg:SI 0 %d0 [182]))) 99 {*addsi3_5200} (insn_list 677 (nil))
(nil))
...
(note 688 687 689 ("yy.c") 640)
(note 689 688 1150 NOTE_INSN_DELETED)
(insn 1150 689 690 (set (reg:SI 0 %d0)
(const_int 1 [0x1])) 30 {*m68k.md:993} (nil)
(nil))
(insn 690 1150 691 (set (mem:SI (plus:SI (reg/f:SI 14 %a6)
(const_int -428 [0xfffffe54])) [0 rotate S4 A16])
(plus:SI (mem:SI (plus:SI (reg/f:SI 14 %a6)
(const_int -428 [0xfffffe54])) [0 rotate S4 A16])
(reg:SI 0 %d0))) 99 {*addsi3_5200} (nil)
(nil))
Hopefully this is enough information. I'm still cutting the testcase
down to size... I hope to have a bug report soon.
--
Peter Barada Peter.Barada@motorola.com
Wizard 781-852-2768 (direct)
WaveMark Solutions(wholly owned by Motorola) 781-270-0193 (fax)