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Re: mips cc1 spec vs. fp reg defines vs. assembly code
- From: Eric Christopher <echristo at redhat dot com>
- To: cgd at broadcom dot com
- Cc: gcc at gcc dot gnu dot org, Neil Booth <neil at daikokuya dot demon dot co dot uk>
- Date: 09 Jun 2002 12:57:46 -0700
- Subject: Re: mips cc1 spec vs. fp reg defines vs. assembly code
- References: <yov5660tcfaw.fsf@broadcom.com>
> But in fact it wasn't so sane after all:
>
> * -mfp64 wasn't being passed to cc1 -- I'd guess because it was doing
> preprocessed assembly, and the -mfp64 was specified in CC1_SPEC --
> and therefore TARGET_FLOAT64 wasn't true.
Hrm.
>
> * __mips_fpr wasn't being defined _at all_, I guess because
> TARGET_CPU_CPP_BUILTINS wasn't being invoked for preprocessed
> assembly?
>
That doesn't sound right. It should be.
Anyhow, here's the in-progress patch for the TARGET_*_CPP_BUILTINS see
if it helps.
-eric
ps. Send me the changes that you made in config.gcc for mipsisa64...
there might be a problem there as well.
--
I will not carve gods
Index: ecoff.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/ecoff.h,v
retrieving revision 1.6
diff -u -p -w -r1.6 ecoff.h
--- ecoff.h 26 Apr 2001 16:02:05 -0000 1.6
+++ ecoff.h 9 Jun 2002 19:49:01 -0000
@@ -24,9 +24,6 @@ Boston, MA 02111-1307, USA. */
#include "mips/mips.h"
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR3000 -D_mips -D_MIPSEB -D_R3000"
-
/* Use memcpy, et. al., rather than bcopy. */
#define TARGET_MEM_FUNCTIONS
Index: ecoffl.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/ecoffl.h,v
retrieving revision 1.3
diff -u -p -w -r1.3 ecoffl.h
--- ecoffl.h 16 Dec 1998 21:08:56 -0000 1.3
+++ ecoffl.h 9 Jun 2002 19:49:01 -0000
@@ -25,6 +25,3 @@ Boston, MA 02111-1307, USA. */
#include "gofast.h"
#include "mips/ecoff.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000"
Index: elf64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/elf64.h,v
retrieving revision 1.42
diff -u -p -w -r1.42 elf64.h
--- elf64.h 18 May 2002 19:27:47 -0000 1.42
+++ elf64.h 9 Jun 2002 19:49:01 -0000
@@ -48,15 +48,6 @@ Boston, MA 02111-1307, USA. */
#include "mips/mips.h"
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000"
-
-/* I would rather put this in CPP_PREDEFINES, but the gcc driver
- doesn't handle -U options in CPP_PREDEFINES. */
-#undef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "\
-%{!mips1:%{!mips2:-U__mips -D__mips=3 -D__mips64}}"
-
/* Use memcpy, et. al., rather than bcopy. */
#define TARGET_MEM_FUNCTIONS
Index: elfl.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/elfl.h,v
retrieving revision 1.2
diff -u -p -w -r1.2 elfl.h
--- elfl.h 16 Dec 1998 21:08:59 -0000 1.2
+++ elfl.h 9 Jun 2002 19:49:01 -0000
@@ -24,6 +24,3 @@ Boston, MA 02111-1307, USA. */
#define TARGET_ENDIAN_DEFAULT 0
#include "mips/elf.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR3000 -D_mips -D_MIPSEL -D_R3000"
Index: elfl64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/elfl64.h,v
retrieving revision 1.2
diff -u -p -w -r1.2 elfl64.h
--- elfl64.h 16 Dec 1998 21:09:00 -0000 1.2
+++ elfl64.h 9 Jun 2002 19:49:01 -0000
@@ -24,6 +24,3 @@ Boston, MA 02111-1307, USA. */
#define TARGET_ENDIAN_DEFAULT 0
#include "mips/elf64.h"
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEL -DR4000 -D_mips -D_MIPSEL -D_R4000"
Index: iris3.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/iris3.h,v
retrieving revision 1.3
diff -u -p -w -r1.3 iris3.h
--- iris3.h 2 Nov 2000 23:29:11 -0000 1.3
+++ iris3.h 9 Jun 2002 19:49:01 -0000
@@ -21,16 +21,16 @@ Boston, MA 02111-1307, USA. */
#define SGI_TARGET 1 /* inform other mips files this is SGI */
/* Names to predefine in the preprocessor for this target machine. */
-
+/* Temporarily #if 0'd until Irix header consolidation. */
+#if 0
#define CPP_PREDEFINES "\
-Dunix -Dmips -Dsgi -DSVR3 -Dhost_mips -DMIPSEB -DSYSTYPE_SYSV \
-Asystem=unix -Asystem=svr3 -Acpu=mips -Amachine=mips"
-
-#define STARTFILE_SPEC "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-
#define SUBTARGET_CPP_SPEC "\
%{!ansi:-D__EXTENSIONS__} -D_MIPSEB -D_SYSTYPE_SYSV"
+#endif
+#define STARTFILE_SPEC "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
#define LIB_SPEC \
"%{!p:%{!pg:%{!static:%{!g*:-lc_s}} -lc}}%{p:-lc_p}%{pg:-lc_p} crtn.o%s"
Index: iris5.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/iris5.h,v
retrieving revision 1.14
diff -u -p -w -r1.14 iris5.h
--- iris5.h 8 Jan 2002 22:51:37 -0000 1.14
+++ iris5.h 9 Jun 2002 19:49:01 -0000
@@ -65,27 +65,6 @@ Boston, MA 02111-1307, USA. */
#undef SUBTARGET_CC1_SPEC
#define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}"
-/* ??? _MIPS_SIM and _MIPS_SZPTR should eventually depend on options when
- options for them exist. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \
- -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \
- -D_MIPS_SIM=_MIPS_SIM_ABI32 -D_MIPS_SZPTR=32 \
- -Asystem=unix -Asystem=svr4 -Acpu=mips -Amachine=sgi"
-
-#undef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC "\
-%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE -D_LONGLONG} \
-%{!mfp64: -D_MIPS_FPSET=16}%{mfp64: -D_MIPS_FPSET=32} \
-%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
-%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
-%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
-%{!mips1: %{!mips2: %{!mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS1}}} \
-%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \
-%{!mlong64: -D_MIPS_SZLONG=32}%{mlong64: -D_MIPS_SZLONG=64}"
-
#undef LINK_SPEC
#define LINK_SPEC "\
%{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
Index: iris6.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/iris6.h,v
retrieving revision 1.48
diff -u -p -w -r1.48 iris6.h
--- iris6.h 19 May 2002 15:23:06 -0000 1.48
+++ iris6.h 9 Jun 2002 19:49:01 -0000
@@ -69,47 +69,65 @@ Boston, MA 02111-1307, USA. */
system header files require it. This is OK, because gcc never warns
when long long is used in system header files. Alternatively, we can
add support for the SGI builtin type __long_long. */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES \
- "-Dunix -Dmips -Dsgi -Dhost_mips -DMIPSEB -D_MIPSEB -DSYSTYPE_SVR4 \
- -D_LONGLONG -D_SVR4_SOURCE -D_MODERN_C -D__DSO__ \
- -Asystem=unix -Asystem=svr4 -Acpu=mips -Amachine=sgi"
-/* We must make -mips3 do what -mlong64 used to do. */
-/* ??? If no mipsX option given, but a mabi=X option is, then should set
- _MIPS_ISA based on the mabi=X option. */
-/* ??? If no mabi=X option give, but a mipsX option is, then should set
- _MIPS_SIM based on the mipsX option. */
-/* ??? Same for _MIPS_SZINT. */
-/* ??? Same for _MIPS_SZPTR. */
+#define TARGET_OS_CPP_BUILTINS() \
+ do { \
+ builtin_define_std ("host_mips"); \
+ builtin_define ("_LONGLONG"); \
+ builtin_define ("_MODERN_C"); \
+ builtin_define ("_SVR4_SOURCE"); \
+ builtin_define_std ("SYSTYPE_SVR4"); \
+ builtin_define ("__DSO__"); \
+ builtin_define_std ("unix"); \
+ builtin_define_std ("sgi"); \
+ builtin_assert ("system=svr4"); \
+ builtin_assert ("system=unix"); \
+ builtin_assert ("machine=sgi"); \
+ \
+ if (mips_abi == ABI_32) \
+ { \
+ builtin_define ("_MIPS_SIM=_MIPS_SIM_ABI32"); \
+ builtin_define ("_MIPS_SZLONG=32"); \
+ builtin_define ("_MIPS_SZPTR=32"); \
+ } \
+ else if (mips_abi == ABI_64) \
+ { \
+ builtin_define ("_ABI64=3"); \
+ builtin_define ("_MIPS_SIM=_ABI64"); \
+ builtin_define ("_MIPS_SZLONG=64"); \
+ builtin_define ("_MIPS_SZPTR=64"); \
+ } \
+ else \
+ { \
+ builtin_define ("_ABIN32=2"); \
+ builtin_define ("_MIPS_SIM=_ABIN32"); \
+ builtin_define ("_MIPS_SZLONG=32"); \
+ builtin_define ("_MIPS_SZPTR=32"); \
+ } \
+ \
+ if (!TARGET_FLOAT64) \
+ builtin_define ("_MIPS_FPSET=16"); \
+ else \
+ builtin_define ("_MIPS_FPSET=32"); \
+ \
+ if (!TARGET_INT64) \
+ builtin_define ("_MIPS_SZINT=32"); \
+ else \
+ builtin_define ("_MIPS_SZINT=64"); \
+ \
+ if (!ISA_MIPS1 && !ISA_MIPS2) \
+ builtin_define ("_COMPILER_VERSION=601"); \
+ \
+ if (c_language == clk_cplusplus) \
+ { \
+ builtin_define ("__EXTENSIONS__"); \
+ builtin_define ("_SGI_SOURCE"); \
+ } \
+} while (0)
+
#undef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC "\
-%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE} \
-%{mfp32: -D_MIPS_FPSET=16}%{!mfp32: -D_MIPS_FPSET=32} \
-%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
-%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
-%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
-%{mips4: -D_MIPS_ISA=_MIPS_ISA_MIPS4} \
-%{!mips*: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
-%{mabi=32: -D_MIPS_SIM=_MIPS_SIM_ABI32} \
-%{mabi=n32: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \
-%{mabi=64: -D_ABI64=3 -D_MIPS_SIM=_ABI64} \
-%{!mabi*: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \
-%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \
-%{mabi=32: -D_MIPS_SZLONG=32} \
-%{mabi=n32: -D_MIPS_SZLONG=32} \
-%{mabi=64: -D_MIPS_SZLONG=64} \
-%{!mabi*: -D_MIPS_SZLONG=32} \
-%{mabi=32: -D_MIPS_SZPTR=32} \
-%{mabi=n32: -D_MIPS_SZPTR=32} \
-%{mabi=64: -D_MIPS_SZPTR=64} \
-%{!mabi*: -D_MIPS_SZPTR=32} \
-%{!mips1:%{!mips2: -D_COMPILER_VERSION=601}} \
-%{!mips*: -U__mips -D__mips=3} \
-%{mabi=32: -U__mips64} \
-%{mabi=n32: -D__mips64} \
-%{mabi=64: -D__mips64} \
-%{!mabi*: -D__mips64}"
+%{!ansi:-D__EXTENSIONS__ -D_SGI_SOURCE}"
/* The GNU C++ standard library requires that __EXTENSIONS__ and
_SGI_SOURCE be defined on at least irix6.2 and probably all irix6
@@ -117,11 +135,6 @@ Boston, MA 02111-1307, USA. */
!ansi, for g++ we want them regardless. We don't need this on
irix6.5 itself, but it shouldn't hurt other than the namespace
pollution. */
-#undef CPLUSPLUS_CPP_SPEC
-#define CPLUSPLUS_CPP_SPEC "\
--D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
-%{ansi:-D__EXTENSIONS__ -D_SGI_SOURCE} %(cpp) \
-"
/* Irix 6 uses DWARF-2. */
#define DWARF2_DEBUGGING_INFO
Index: linux.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/linux.h,v
retrieving revision 1.45
diff -u -p -w -r1.45 linux.h
--- linux.h 29 May 2002 18:18:43 -0000 1.45
+++ linux.h 9 Jun 2002 19:49:02 -0000
@@ -127,66 +127,54 @@ void FN () \
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_ABICALLS|MASK_GAS)
-/* Specify predefined symbols in preprocessor. */
-#undef CPP_PREDEFINES
-#if TARGET_ENDIAN_DEFAULT == 0
-#define CPP_PREDEFINES "-DMIPSEL -D_MIPSEL -Dunix -Dmips -D_mips \
--DR3000 -D_R3000 -D__gnu_linux__ -Dlinux -Asystem=posix -Acpu=mips \
--Amachine=mips -D__ELF__ -D__PIC__ -D__pic__"
-#else
-#define CPP_PREDEFINES "-DMIPSEB -D_MIPSEB -Dunix -Dmips -D_mips \
--DR3000 -D_R3000 -D__gnu_linux__ -Dlinux -Asystem=posix -Acpu=mips \
--Amachine=mips -D__ELF__ -D__PIC__ -D__pic__"
-#endif
+#define TARGET_OS_CPP_BUILTINS() \
+ do { \
+ builtin_define ("__gnu_linux__"); \
+ builtin_define ("__ELF__"); \
+ builtin_define ("__PIC__"); \
+ builtin_define ("__pic__"); \
+ builtin_define_std ("unix"); \
+ builtin_define_std ("linux"); \
+ builtin_assert ("system=linux"); \
+ /* The GNU C++ standard library requires this. */ \
+ if (c_language = clk_cplusplus) \
+ builtin_define ("_GNU_SOURCE"); \
+ \
+ if (mips_abi == ABI_N32) \
+ { \
+ builtin_define ("_ABIN32=2"); \
+ builtin_define ("_MIPS_SIM=_ABIN32"); \
+ builtin_define ("_MIPS_SZLONG=32"); \
+ builtin_define ("_MIPS_SZPTR=32"); \
+ } \
+ else if (mips_abi == ABI_64) \
+ { \
+ builtin_define ("_ABI64=3"); \
+ builtin_define ("_MIPS_SIM=_ABI64"); \
+ builtin_define ("_MIPS_SZLONG=64"); \
+ builtin_define ("_MIPS_SZPTR=64"); \
+ } \
+ else \
+ { \
+ builtin_define ("_MIPS_SIM=_MIPS_SIM_ABI32"); \
+ builtin_define ("_MIPS_SZLONG=32"); \
+ builtin_define ("_MIPS_SZPTR=32"); \
+ } \
+ if (TARGET_FLOAT64) \
+ builtin_define ("_MIPS_FPSET=32"); \
+ else \
+ builtin_define ("_MIPS_FPSET=16"); \
+ \
+ if (TARGET_INT64) \
+ builtin_define ("_MIPS_SZINT=64"); \
+ else \
+ builtin_define ("_MIPS_SZINT=32"); \
+} while (0)
-/* We must make -mips3 do what -mlong64 used to do. */
-/* ??? If no mipsX option given, but a mabi=X option is, then should set
- _MIPS_ISA based on the mabi=X option. */
-/* ??? If no mabi=X option give, but a mipsX option is, then should set
- _MIPS_SIM based on the mipsX option. */
-/* ??? Same for _MIPS_SZINT. */
-/* ??? Same for _MIPS_SZPTR. */
-#undef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC "\
-%{mfp32: -D_MIPS_FPSET=16} \
-%{mfp64: -D_MIPS_FPSET=32} \
-%{!mfp*: -D_MIPS_FPSET=32} \
-%{mips1: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
-%{mips2: -D_MIPS_ISA=_MIPS_ISA_MIPS2} \
-%{mips3: -D_MIPS_ISA=_MIPS_ISA_MIPS3} \
-%{mips4: -D_MIPS_ISA=_MIPS_ISA_MIPS4} \
-%{mips5: -D_MIPS_ISA=_MIPS_ISA_MIPS5} \
-%{mips32: -D_MIPS_ISA=_MIPS_ISA_MIPS32} \
-%{mips64: -D_MIPS_ISA=_MIPS_ISA_MIPS64} \
-%{!mips*: -D_MIPS_ISA=_MIPS_ISA_MIPS1} \
-%{mabi=32: -D_MIPS_SIM=_MIPS_SIM_ABI32} \
-%{mabi=n32: -D_ABIN32=2 -D_MIPS_SIM=_ABIN32} \
-%{mabi=64: -D_ABI64=3 -D_MIPS_SIM=_ABI64} \
-%{!mabi*: -D_MIPS_SIM=_MIPS_SIM_ABI32} \
-%{!mint64: -D_MIPS_SZINT=32}%{mint64: -D_MIPS_SZINT=64} \
-%{mabi=32: -D_MIPS_SZLONG=32} \
-%{mabi=n32: -D_MIPS_SZLONG=32} \
-%{mabi=64: -D_MIPS_SZLONG=64} \
-%{!mabi*: -D_MIPS_SZLONG=32} \
-%{mabi=32: -D_MIPS_SZPTR=32} \
-%{mabi=n32: -D_MIPS_SZPTR=32} \
-%{mabi=64: -D_MIPS_SZPTR=64} \
-%{!mabi*: -D_MIPS_SZPTR=32} \
-%{!mips*: -U__mips -D__mips} \
-%{mabi=32: -U__mips64} \
-%{mabi=n32: -D__mips64} \
-%{mabi=64: -U__mips64} \
-%{!mabi*: -U__mips64} \
%{fno-PIC:-U__PIC__ -U__pic__} %{fno-pic:-U__PIC__ -U__pic__} \
%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} \
%{pthread:-D_REENTRANT}"
-
-/* The GNU C++ standard library requires that these macros be defined. */
-#undef CPLUSPLUS_CPP_SPEC
-#define CPLUSPLUS_CPP_SPEC "\
--D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
--D_GNU_SOURCE %(cpp) \
-"
/* From iris5.h */
/* -G is incompatible with -KPIC which is the default, so only allow objects
Index: mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.188
diff -u -p -w -r1.188 mips.h
--- mips.h 6 Jun 2002 01:25:15 -0000 1.188
+++ mips.h 9 Jun 2002 19:49:05 -0000
@@ -321,6 +321,14 @@ extern void sbss_section PARAMS ((void)
/* Generate mips16 code */
#define TARGET_MIPS16 (target_flags & MASK_MIPS16)
+/* Generic ISA defines. */
+#define ISA_MIPS1 (mips_isa == 1)
+#define ISA_MIPS2 (mips_isa == 2)
+#define ISA_MIPS3 (mips_isa == 3)
+#define ISA_MIPS4 (mips_isa == 4)
+#define ISA_MIPS32 (mips_isa == 32)
+#define ISA_MIPS64 (mips_isa == 64)
+
/* Architecture target defines. */
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
#define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
@@ -336,6 +344,122 @@ extern void sbss_section PARAMS ((void)
#define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
+/* Target CPU builtins. */
+#define TARGET_CPU_CPP_BUILTINS() \
+ do \
+ { \
+ builtin_assert ("cpu=mips"); \
+ builtin_define_std ("mips"); \
+ builtin_define ("_mips"); \
+ \
+ if (TARGET_64BIT) \
+ { \
+ builtin_define ("__mips64"); \
+ /* Silly, but will do until processor defines. */ \
+ builtin_define_std ("R4000"); \
+ builtin_define ("_R4000"); \
+ } \
+ else \
+ { \
+ builtin_define ("__mips"); \
+ /* Ditto. */ \
+ builtin_define_std ("R3000"); \
+ builtin_define ("_R3000"); \
+ } \
+ if (TARGET_FLOAT64) \
+ builtin_define ("__mips_fpr=64"); \
+ else \
+ builtin_define ("__mips_fpr=32"); \
+ \
+ if (TARGET_MIPS16) \
+ builtin_define ("__mips16"); \
+ \
+ if (ISA_MIPS1) \
+ { \
+ builtin_define ("__mips=1"); \
+ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
+ } \
+ else if (ISA_MIPS2) \
+ { \
+ builtin_define ("__mips=2"); \
+ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
+ } \
+ else if (ISA_MIPS3) \
+ { \
+ builtin_define ("__mips=3"); \
+ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
+ } \
+ else if (ISA_MIPS4) \
+ { \
+ builtin_define ("__mips=4"); \
+ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
+ } \
+ else if (ISA_MIPS32) \
+ { \
+ builtin_define ("__mips=32"); \
+ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
+ } \
+ else if (ISA_MIPS64) \
+ { \
+ builtin_define ("__mips=64"); \
+ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
+ } \
+ \
+ if (TARGET_HARD_FLOAT) \
+ builtin_define ("__mips_hard_float"); \
+ else if (TARGET_SOFT_FLOAT) \
+ builtin_define ("__mips_soft_float"); \
+ \
+ if (TARGET_SINGLE_FLOAT) \
+ builtin_define ("__mips_single_float"); \
+ \
+ if (TARGET_LONG64) \
+ builtin_define ("__LONG_MAX__=9223372036854775807L"); \
+ \
+ if (TARGET_BIG_ENDIAN) \
+ { \
+ builtin_define_std ("MIPSEB"); \
+ builtin_define ("_MIPSEB"); \
+ } \
+ else \
+ { \
+ builtin_define_std ("MIPSEL"); \
+ builtin_define ("_MIPSEL"); \
+ } \
+ \
+ /* Macros dependent on the C dialect. */ \
+ if (preprocessing_asm_p ()) \
+ { \
+ builtin_define_std ("LANGUAGE_ASSEMBLY"); \
+ builtin_define_std ("_LANGUAGE_ASSEMBLY"); \
+ } \
+ else if (c_language == clk_c) \
+ { \
+ builtin_define_std ("LANGUAGE_C"); \
+ builtin_define_std ("_LANGUAGE_C"); \
+ } \
+ else if (c_language == clk_cplusplus) \
+ { \
+ builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
+ builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
+ builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
+ } \
+ else if (c_language == clk_objective_c) \
+ { \
+ builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
+ builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
+ /* Bizzare, but needed at least for Irix. */ \
+ builtin_define_std ("LANGUAGE_C"); \
+ builtin_define ("_LANGUAGE_C"); \
+ } \
+ \
+ if (mips_abi == ABI_EABI) \
+ builtin_define ("__mips_eabi"); \
+ \
+} while (0)
+
+
+
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
@@ -585,8 +709,8 @@ extern void sbss_section PARAMS ((void)
/* Generate three-operand multiply instructions for SImode. */
#define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
- || mips_isa == 32 \
- || mips_isa == 64) \
+ || ISA_MIPS32 \
+ || ISA_MIPS64) \
&& !TARGET_MIPS16)
/* Generate three-operand multiply instructions for DImode. */
@@ -597,23 +721,23 @@ extern void sbss_section PARAMS ((void)
depending on the instruction set architecture level. */
#define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
-#define HAVE_SQRT_P() (mips_isa != 1)
+#define HAVE_SQRT_P() (!ISA_MIPS1)
/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
-#define ISA_HAS_64BIT_REGS (mips_isa == 3 \
- || mips_isa == 4 \
- || mips_isa == 64)
+#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
+ || ISA_MIPS4 \
+ || ISA_MIPS64)
/* ISA has branch likely instructions (eg. mips2). */
/* Disable branchlikely for tx39 until compare rewrite. They haven't
been generated up to this point. */
-#define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
+#define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
&& ! TARGET_MIPS16)
/* ISA has the conditional move instructions introduced in mips4. */
-#define ISA_HAS_CONDMOVE ((mips_isa == 4 \
- || mips_isa == 32 \
- || mips_isa == 64) \
+#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
+ || ISA_MIPS32 \
+ || ISA_MIPS64) \
&& ! TARGET_MIPS16)
/* ISA has just the integer condition move instructions (movn,movz) */
@@ -621,37 +745,37 @@ extern void sbss_section PARAMS ((void)
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
-#define ISA_HAS_8CC (mips_isa == 4 \
- || mips_isa == 32 \
- || mips_isa == 64)
+#define ISA_HAS_8CC (ISA_MIPS4 \
+ || ISA_MIPS32 \
+ || ISA_MIPS64)
/* This is a catch all for the other new mips4 instructions: indexed load and
indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
and the FP recip and recip sqrt instructions */
-#define ISA_HAS_FP4 (mips_isa == 4 \
+#define ISA_HAS_FP4 (ISA_MIPS4 \
&& ! TARGET_MIPS16)
/* ISA has conditional trap instructions. */
-#define ISA_HAS_COND_TRAP (mips_isa >= 2 \
+#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
&& ! TARGET_MIPS16)
/* ISA has multiply-accumulate instructions, madd and msub. */
-#define ISA_HAS_MADD_MSUB ((mips_isa == 32 \
- || mips_isa == 64 \
+#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
+ || ISA_MIPS64 \
) && ! TARGET_MIPS16)
/* ISA has nmadd and nmsub instructions. */
-#define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
+#define ISA_HAS_NMADD_NMSUB (ISA_MIPS4 \
&& ! TARGET_MIPS16)
/* ISA has count leading zeroes/ones instruction (not implemented). */
-#define ISA_HAS_CLZ_CLO ((mips_isa == 32 \
- || mips_isa == 64 \
+#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
+ || ISA_MIPS64 \
) && ! TARGET_MIPS16)
/* ISA has double-word count leading zeroes/ones instruction (not
implemented). */
-#define ISA_HAS_DCLZ_DCLO (mips_isa == 64 \
+#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
&& ! TARGET_MIPS16)
/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
@@ -761,14 +885,6 @@ while (0)
#endif
-/* Names to predefine in the preprocessor for this target machine. */
-
-#ifndef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
--D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
--Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
-#endif
-
/* Assembler specs. */
/* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
@@ -954,119 +1070,13 @@ extern int mips_abi;
/* Preprocessor specs. */
-/* Rules for SIZE_TYPE and PTRDIFF_TYPE are:
-
- both gp64 and long64 (not the options, but the corresponding flags,
- so defaults came into play) are required in order to have `long' in
- SIZE_TYPE and PTRDIFF_TYPE.
-
- on eabi, -mips1, -mips2 and -mips32 disable gp64, whereas mips3,
- -mips4, -mips5 and -mips64 enable it.
-
- on other ABIs, -mips* options do not affect gp32/64, but the
- default ISA affects the default gp size.
-
- -mgp32 disables gp64, whereas -mgp64 enables it.
-
- on eabi, gp64 implies long64.
-
- -mlong64, and -mabi=64 are the only other ways to enable long64.
-
-*/
-
-#if MIPS_ISA_DEFAULT != 3 && MIPS_ISA_DEFAULT != 4 && MIPS_ISA_DEFAULT != 5 && MIPS_ISA_DEFAULT != 64
-
-/* 32-bit cases first. */
-
-#if MIPS_ABI_DEFAULT == ABI_EABI
-#define LONG_MAX_SPEC "\
-%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
-%{!mlong64:\
- %{mabi=eabi|!mabi=*:\
- %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
- %{mips3|mips4|mips5|mips64|mgp64: \
- -D__LONG_MAX__=9223372036854775807L}}}}}}}} \
-"
-#else /* ABI_DEFAULT != ABI_EABI */
-#define LONG_MAX_SPEC "\
-%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
-%{!mlong64:\
- %{mabi=eabi:\
- %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
- %{mips3|mips4|mips5|mips64|mgp64: \
- -D__LONG_MAX__=9223372036854775807L}}}}}}}} \
-"
-#endif
-
-#else
-
-/* 64-bit default ISA. */
-#if MIPS_ABI_DEFAULT == ABI_EABI
-#define LONG_MAX_SPEC "\
-%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
-%{!mlong64:\
- %{mabi=eabi|!mabi=*:\
- %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
- -D__LONG_MAX__=9223372036854775807L}}}}}}}\
-"
-#else /* ABI_DEFAULT != ABI_EABI */
-#define LONG_MAX_SPEC "\
-%{mlong64:-D__LONG_MAX__=9223372036854775807L}\
-%{!mlong64:\
- %{mabi=eabi:\
- %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
- -D__LONG_MAX__=9223372036854775807L}}}}}}}\
-"
-#endif
-
-#endif
-
/* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
overridden by subtargets. */
#ifndef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC ""
#endif
-/* Define appropriate macros for fpr register size. */
-#ifndef CPP_FPR_SPEC
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_FLOAT64)
-#define CPP_FPR_SPEC "-D__mips_fpr=64"
-#else
-#define CPP_FPR_SPEC "-D__mips_fpr=32"
-#endif
-#endif
-
-/* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
- of the source file extension. */
-#undef CPLUSPLUS_CPP_SPEC
-#define CPLUSPLUS_CPP_SPEC "\
--D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
-%(cpp) \
-"
-/* CPP_SPEC is the set of arguments to pass to the preprocessor. */
-
-#ifndef CPP_SPEC
-#define CPP_SPEC "\
-%{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
-%{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
-%{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
-%(subtarget_cpp_size_spec) \
-%{mips3:-U__mips -D__mips=3 -D__mips64} \
-%{mips4:-U__mips -D__mips=4 -D__mips64} \
-%{mips32:-U__mips -D__mips=32} \
-%{mips64:-U__mips -D__mips=64 -D__mips64} \
-%{mgp32:-U__mips64} %{mgp64:-D__mips64} \
-%{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \
-%{msingle-float:%{!msoft-float:-D__mips_single_float}} \
-%{m4650:%{!msoft-float:-D__mips_single_float}} \
-%{msoft-float:-D__mips_soft_float} \
-%{mabi=eabi:-D__mips_eabi} \
-%{mips16:%{!mno-mips16:-D__mips16}} \
-%{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
-%{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
-%(long_max_spec) \
-%(subtarget_cpp_spec) "
-#endif
+#define CPP_SPEC "%(subtarget_cpp_spec)"
/* This macro defines names of additional specifications to put in the specs
that can be used in various specifications like CC1_SPEC. Its definition
@@ -1082,8 +1092,6 @@ extern int mips_abi;
{ "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
{ "cc1_cpu_spec", CC1_CPU_SPEC}, \
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
- { "long_max_spec", LONG_MAX_SPEC }, \
- { "cpp_fpr_spec", CPP_FPR_SPEC }, \
{ "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
{ "gas_asm_spec", GAS_ASM_SPEC }, \
{ "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, \
@@ -2302,7 +2310,7 @@ extern enum reg_class mips_char_to_class
: current_function_outgoing_args_size)
#endif
-/* The return address for the current frame is in r31 is this is a leaf
+/* The return address for the current frame is in r31 if this is a leaf
function. Otherwise, it is on the stack. It is at a variable offset
from sp/fp/ap, so we define a fake hard register rap which is a
poiner to the return address on the stack. This always gets eliminated
Index: mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.129
diff -u -p -w -r1.129 mips.md
--- mips.md 6 Jun 2002 01:25:16 -0000 1.129
+++ mips.md 9 Jun 2002 19:49:08 -0000
@@ -1793,8 +1793,8 @@
if (which_alternative == 1)
return \"mult\\t%1,%2\";
if (TARGET_MAD
- || mips_isa == 32
- || mips_isa == 64)
+ || ISA_MIPS32
+ || ISA_MIPS64)
return \"mul\\t%0,%1,%2\";
return \"mult\\t%0,%1,%2\";
}"
@@ -10529,8 +10529,6 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
"
{
- if (mips_isa == 32)
- FAIL;
gen_conditional_move (operands);
DONE;
}")
Index: netbsd.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/netbsd.h,v
retrieving revision 1.20
diff -u -p -w -r1.20 netbsd.h
--- netbsd.h 8 Jun 2002 17:23:40 -0000 1.20
+++ netbsd.h 9 Jun 2002 19:49:08 -0000
@@ -67,7 +67,6 @@ Boston, MA 02111-1307, USA. */
#undef US_SOFTWARE_GOFAST
#undef INIT_SUBTARGET_OPTABS
#define INIT_SUBTARGET_OPTABS
-#undef CPP_PREDEFINES
/* Get generic NetBSD definitions. */
@@ -78,42 +77,6 @@ Boston, MA 02111-1307, USA. */
#include <netbsd-elf.h>
-/* Provide a CPP_SPEC appropriate for NetBSD. This is a simplified
- CPP_SPEC from <mips/mips.h>. We (mostly) use the SUBTARGET_CPP_SPEC
- to deal with NetBSD-specific CPP options.
-
- We default to MIPS-I at the very beginning of the spec, and let the
- value get overridden later, as necessary. We also set up a default
- endian spec.
-
- This will get cleaned up once the MIPS target uses
- TARGET_CPU_CPP_BUILTINS(). */
-
-#undef CPP_SPEC
-#define CPP_SPEC \
- "-D__mips=1 \
- %(subtarget_cpp_size_spec) \
- %{mips3:-U__mips -D__mips=3 -D__mips64} \
- %{mips4:-U__mips -D__mips=4 -D__mips64} \
- %{mips32:-U__mips -D__mips=32} \
- %{mips64:-U__mips -D__mips=64 -D__mips64} \
- %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
- %{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} \
- %{!mfp32: \
- %{!mfp64: \
- %{mgp32:-D__mips_fpr=32} \
- %{!mgp32: %(cpp_fpr_spec)}}} \
- %{msingle-float: \
- %{!msoft-float:-D__mips_single_float}} \
- %{m4650: \
- %{!msoft-float:-D__mips_single_float}} \
- %{msoft-float:-D__mips_soft_float} \
- %{mabi=eabi:-D__mips_eabi} \
- %{mips16:%{!mno-mips16:-D__mips16}} \
- %{EB:-D__MIPSEB__} %{EL:-D__MIPSEL__} \
- %{!EB:%{!EL:%(subtarget_endian_default)}} \
- %(subtarget_cpp_spec) "
-
/* Extra specs we need. */
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \
Index: rtems.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/rtems.h,v
retrieving revision 1.4
diff -u -p -w -r1.4 rtems.h
--- rtems.h 12 Apr 2002 13:34:56 -0000 1.4
+++ rtems.h 9 Jun 2002 19:49:08 -0000
@@ -21,6 +21,8 @@ Boston, MA 02111-1307, USA. */
/* Specify predefined symbols in preprocessor. */
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -D_mips -D_MIPSEB \
- -D__rtems__ -Asystem=rtems"
+#define TARGET_OS_CPP_BUILTINS() \
+do { \
+ builtin_define ("__rtems__"); \
+ builtin_assert ("system=rtems"); \
+} while (0)
Index: rtems64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/rtems64.h,v
retrieving revision 1.16
diff -u -p -w -r1.16 rtems64.h
--- rtems64.h 18 May 2002 19:27:47 -0000 1.16
+++ rtems64.h 9 Jun 2002 19:49:08 -0000
@@ -20,10 +20,11 @@ the Free Software Foundation, 59 Temple
Boston, MA 02111-1307, USA. */
/* Specify predefined symbols in preprocessor. */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dmips -DMIPSEB -DR4000 -D_mips -D_MIPSEB -D_R4000 \
- -D__rtems__ -Asystem=rtems"
+#define TARGET_OS_CPP_BUILTINS() \
+do { \
+ builtin_define ("__rtems__"); \
+ builtin_assert ("system=rtems"); \
+} while (0)
#undef EXTRA_SECTIONS
#define EXTRA_SECTIONS in_sdata