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Re: Alpha CPU-specific builtins


On Thu, May 30, 2002 at 09:20:11PM +0200, Falk Hueffner wrote:
> > (define_insn "uminv8qi3"
> >   [(set (match_operand:V8QI 0 "register_operand" "=r")
> > 	(umin:V8QI (match_operand:V8QI "reg_or_0_operand" "rJ")
> > 		   (match_operand:V8QI "reg_or_0_operand" "rJ")))]
> 
>                                       ^ missing 1 and 2 here, right?

Yes.

> I get
> 
> x.c:2: unrecognizable insn:
> (insn 13 5 18 (set (subreg:V8QI (reg:DI 71) 0)
>         (umin:V8QI (subreg:V8QI (reg/v:DI 70) 0)
>             (const_vector:V8QI[ 
>                     (const_int 0 [0x0])
>                     (const_int 0 [0x0])
>                     (const_int 0 [0x0])
>                     (const_int 0 [0x0])
>                     (const_int 0 [0x0])
>                     (const_int 0 [0x0])
>                     (const_int 0 [0x0])
>                     (const_int 0 [0x0])
>                 ] ))) -1 (insn_list 4 (nil))
>     (expr_list:REG_DEAD (reg/v:DI 70)
>         (nil)))

reg_or_0_operand should use CONST0_RTX (mode) instead of const0_rtx.
Also, PREDICATE_CODES for reg_or_0_operand should be extended to
include CONST_DOUBLE and CONST_VECTOR.

> Also, with this formulation, minub8 won't ever be emitted with an
> immediate, right?

Correct.

> (Not that I could think of any reasonable application for an
> immediate != 0 here, but...)

Neither could I.


r~


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