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Re: java aliasing rules
- From: Richard Henderson <rth at redhat dot com>
- To: Jeff Sturm <jsturm at one-point dot com>
- Cc: Bryce McKinlay <bryce at waitaki dot otago dot ac dot nz>, tromey at redhat dot com, Dan Nicolaescu <dann at godzilla dot ics dot uci dot edu>, java at gcc dot gnu dot org, gcc at gcc dot gnu dot org
- Date: Sat, 30 Mar 2002 13:55:03 -0800
- Subject: Re: java aliasing rules
- References: <3CA4F734.6040706@waitaki.otago.ac.nz> <Pine.LNX.4.10.10203300926250.5677-100000@mars.deadcafe.org>
On Sat, Mar 30, 2002 at 09:35:54AM -0500, Jeff Sturm wrote:
> Wouldn't accessing r9 immediately after the load cause a pipeline stall?
Yes.
> Come to think of it, what happens on an out-of-order processor (e.g.
> Alpha EV6) when an instruction traps? Are preceding instructions
> guaranteed to have completed? I'm curious.
Yes. All the instructions before hand are committed, and all
of the in-flight instruction after are aborted.
r~