[Slightly OT] Automatic Generation of GCC md

[Soubhik Bhattacharya <soubhik at cse dot iitk dot ac dot in>]

hi all!!
i just want to tell you about the work i've done for my master's
thesis. i've written a tool that generates a part of GCC machine
description, from Sim-nML processor specification.

Sim-nML is a high-level processor specification language. it views a
processor as a machine that executes a set of instructions. syntax, image,
functionality (side-effect), resource-usage and timing of each instruction
are described in a hierarchical form. the idea is that we want to enable
hardware/software codesign by automatically generating assembler,
disassembler, code generator, simulator, hardware synthesizer etc from a
Sim-nML specification. u may find more info about Sim-nML at
http://www.cse.iitk.ac.in/sim-nml/

we've already written tools for generation of assembler, disassembler,
functional simulator etc. this work tries to complement Sim-nML by
allowing code-generation from Sim-nML.

a brief description of our approach:
an action sequence of an instruction is a sequence of C-like statements
which describe its functionality. an action sequence is simplified using
techniques (many are well-know compiler optimizatins) such as temporary
removal, constant folding, branch elimination, instruction splitting, code
motion etc. after simplifications we did pattern matching to recognize an
instruction with a standard name (similar to the names used in GCC md, but
sans machine mode, ie `add' instead of `addsi3'). some analysis of
addressing modes and registers are also performed. at his point we've
actually gathered enough info for so called `instruction selection'. with
this we generated an md file, and a few macro definitions 
(FIRST_PSEUDO_REGISTER, FIXED_REGISTERS, register class macros, addressing
mode macros etc).

we have generated machine descriptions from Sim-nML
specifications of UltraSparc IIi (sparc64 cpu), PowerPC 603, MIPS
R10000. with some additional human effort (10 person-days) a minimal GCC
port for Sparc has been built. our GCC supports a subset of C-- integer
arith-logic, sequence, control transfer, data movement.

i've kept a draft of my thesis at 
http://alumni.cse.iitk.ac.in/~soubhik.bhattacharya
this'll give you more details. sources will be made public soon.
your views are most welcome.....

With Best Regards,
soubhik.