Re: peephole vs. scheduler

[Joern Rennecke <amylaar at redhat dot com>]

> The instructions I want to combine aren't created until the reload 
> phase, so I don't think this will work.  Let me expand on the problem.  
> Loading FP constants into FP regs, the rs6k compiler produces something 
> like this:
> 
> lis r4,ha16(LC0)
> la r12,lo16(LC0)(r4)
> lfd f7,0(r12)
> 
> It could produce:
> 
> lis r4,ha16(LC0)
> lfd f7,lo16(LC0)(r4)
> 
> I can make it generate high/lo_sum early, but this has no effect; the 
> reload code keys off the REG_EQUIV, and ignores the rtl that's there.  

I suppose you could do this using LEGITIMIZE_RELOAD_ADDRESS to split
the constant address into high and low part, like the sparc port does.

Or you could pretend that FP constants can be loaded directly, using a
scratch register, and fix this up with a peephole2 or in
MACHINE_DEPENDENT_REORG.
You have then the additional opportunity to find three or more FP constant
loads in a row, and use two instructions to load the address of a small
memory region where you can address all of these FP constants.