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Re: cross gcc port problem


Hello Alan,

> The first problem is most likely patterns that in their worst case will
require
> three memory references, and you only have two available scratch index
registers.
    Can you explain what exactly do you mean? This processor and associated
patterns has only one memory reference at a time. The most patterns on this
machine is in the form "accumulator = accumulator op memory".

> You can find out more about the possible reasons by running the compiler
under gdb and
> doing
>
> call debug_reload()
>
> when it aborts with the spill failure (If I recall correctly, this abort()
is in the middle of dealing
> with reloads.
    Ok, I will try this.

> You might also look at the LEGITIMIZE_RELOAD_ADDRESS macro.  You may be
able to "guide"
> the compiler to generating better code for your machine.
    Ok, I will examine this.

> No.  That won't work, because  you CAN'T have any instructions between the
CC setter
> and the CC consumer or the compiler will crash.
    You mean "any instructions" in the gcc sence? Insns? To be more clear
here is the full definition of cmpqi insn:

(define_insn "cmpqi"
  [(set (cc0)
        (compare (match_operand:QI 0 "register_operand" "r")
                 (match_operand:QI 1 "general_operand" "m")))
   (clobber (reg:QI 0))]
""
"
    sub %1")

    So code, which compares accumulator (register) operand with the memory
constant looks like this:

    sub    r1:2    ; compare
    bnea   L5      ; branch not zero

    As you see there is no any extra CC setter before the branch insns. For
now I'm using pattern like this -

(define_insn "cmpqi"
  [(set (cc0)
        (compare (match_operand:QI 0 "register_operand" "r")
                 (match_operand:QI 1 "general_operand" "m")))]
""
"
    sub %1")

    There is no clobber, so port works fine. But I'm not sure this safe
because of one thing - if gcc decides to use reg:QI 0 - accumulator register
for variable storing this code could destroy the content of it.

Thanks for your suggestions,
    Oleg.


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