Re: cross gcc port problem

[Hans-Peter Nilsson <hans-peter dot nilsson at axis dot com>]

> From: "Oleg I. Vdovikin" <vdovikin@jscc.ru>
> Date: Sun, 18 Mar 2001 18:19:38 +0300

Sorry, can't help you with your first problem.  Any of many
possible errors in the port register class description and
generally the port register description can cause this.  (Let's
not assume it's a core gcc bug for the moment. ;-)

>     And the second problem is the absence of the "compare" instructions in
> this processor. So I've defined this operation with substraction
> instructions, but as side effect my compare instruction alters the
> accumulator register, so I've tried to write something like:
> (define_insn "cmpqi"
>   [(set (cc0)
>         (compare (match_operand:QI 0 "register_operand" "r")
>                  (match_operand:QI 1 "general_operand" "m")))
>    (clobber (reg:QI 0))]
>     but again has no luck. :-(( Because gcc "performs" this insn in parallel
> and the only valid operand also comes in reg:QI 0, gcc aborts. So, can
> anyone advise me how to specify clobbering correctly?

Try having a "define_expand" for this.  Alternatively, you might
want to look into defining the "cbranchsi4" and "cmov" patterns.
Though I think only the thumb-within-arm target uses it, and it's
unfortunately not documented.  See also
<URL:http://gcc.gnu.org/ml/gcc/2001-01/msg01806.html> with follow-ups.

brgds, H-P