cross gcc-2.95.2 for ARM

[bkohlen at intrinsyc dot com]

Apologies in advance, if I am addressing the wrong forum.

I have successfully created a complete cross ARM toolchain with
binutils-2.10, gcc-2.95.2 and glibc-2.1.3.  My organization previously
used a very similar toolchain compiled by an individual who has since
left and cannot be contacted.  It was binutils-2.9.5.0.42, gcc-2.95.2
and glibc-2.1.2.

The old toolchain would compile a 16 bit write, such as:
u_int16_t *addr, x;
...
*addr = x;
...
as an ldrh (load register halfword) instruction, which was good, because
the hardware we were writing modules for could only handle 16 bit
transfers, but when looking at two sections of disassembled code, the
new toolchain seems to replace that one instruction with two ldrb (load
register byte) instructions, which is bad, for the same reason ldrh is
good.

I compiled gcc with --target=arm-linux.

Is there anything I can do when compiling gcc to correct this, or should
I be talking to the binutils developers?

TIA,
Ben