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Re: Number of registers on x86

dewar wrote:

> Hmmm! Perhaps Geert Bosch can settle this because he knows these specs
> very well, but my impression was most certainly that register renaming
> is implemented on the Pentium, and that this is where the figure of
> 40 comes from (I have known that figure from long before when the P4
> was announced).
> Toshi said
> ---------
> The IA32 likewise also encompasses a class of processors rather than a
> single implementation, so I believe this is an inaccurate statement.
> The 8086, 80186, 80286, 80386, 80486, and Pentium all are in-order execution
> processors, so therefore they do not use register renaming at all.
> The Pentium Pro and its derivatives (P2 and P3) and also the P4 have
> out-of-order execution capability and use hardware register renaming.

No. The Pentium does not.

The Pentium is an in-order superscalar (dual-issue) implementation of the
IA32 architecture.

To quote from the Intel Architecture Optimization Manual:

"Section 2.1 The Pentium Processor

 The Pentium procesor is an advanced superscalar processor. It is built
 around two general purpose integer pipelines and a pipelined floating
 point unit. The Pentium processor can execute two integer instructions
 simultaneously. A software-transparent dynamic branch prediction
 mechanism minimizes pipeline stalls due to branches."

The Pentium Pro section of the same manual states:

"Section 2.2  The Pentium Pro Processor

 The Pentium Pro processor family uses a dynamic execution architecture
 that blends out-of-order and speculative execution with hardware 
 register renaming and branch prediction.", etc.

(full manual available at:

Basically, out-of-order execution/register renaming was not implemented
on IA32 processors prior to the Pentium Pro.

> Also, out of order execution and register renaming are really rather
> different issues, I am not sure why you are tying them together like
> that.

This should be obvious, but on an architecture such as the IA32 with an
extremely limited register file, it's pointless to implement out-of-order
execution without register renaming.

The register renaming allows the out-of-order design to work effectively
because it eliminates false data dependencies between instructions which
use the same register.

Likewise, it would be pointless to implement register renaming without
out-of-order execution on an IA32 implementation because the processor
would be unable issue new instructions while waiting for data dependencies
to resolve. (stated somewhat awkwardly, but hopefully it's intelligible)


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