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Re: FWD: FLOATING-POINT CONSISTENCY, -FFLOAT-STORE, AND X86
Toon Moene <toon@moene.indiv.nluug.nl> writes:
> Harvey J. Stein wrote:
> >
> > Toon Moene <toon@moene.indiv.nluug.nl> writes:
> >
> > > I must say that I am *not* amused. This discussion goes into a
> > > direction that will leave us with a compiler that, although
> > > numerical-politically correct, will be generating such slow code as
> > > to be totally unuseable.
> >
> > Do you really think it'll make it that much slower? If you're doing
> > computations, how much time is spent dumping & restoring FP registers?
> > Is dumping 10 bytes instead of 8 bytes (current practice) going to
> > have a substantial impact in total run time? You've mentioned in
> > other posts a factor of 2, as if because it's 16 byte aligned it has
> > to move 16 bytes of data. But even if it's 16 byte aligned, it's
> > still only 10 bytes of data, so why should it take 2x as long?
>
> For a thoroughly 32-bit application like mine, 16-byte spills are four
> times as large as necessary - and yes, having all this data move in and
> out of registers does have a cost (think cache footprint).
That's true, but, like I said, it's 10 byte, not 16 byte, and it's vs
the current 8 byte. There's currently no option of doing 4 byte
spills.
--
Harvey J. Stein
BFM Financial Research
hjstein@bfr.co.il