Re: Incrementing volatiles?

["Philippe De Muyter" <phdm at macqel dot be>]

> |> Sorry to be slightly off-topic, but this discussion reminds me a problem
> |> I encountered some months ago when writing a driver for a VME board in
> |> an AIX powerpc environment.  Although I had declared all the registers
> |> of the chips on the board as volatile, and compiled my driver with gcc,
> |> I saw with a logic analyser on the VME bus that the accesses to the
> |> register on the board were not done in the order I had written them.
> |> To solve that problem, I had to manually add asm("eieio") after each
> |> access to a volatile register.  Should gcc not do that for me ?
> 
> I don't think so.  It's the responsibility of the system software to
> make sure that accesses to hardware registers are uncached and serialized.

Actually, the accesses were uncached, but the powerpc processor itself
does not respect the order of the instructions for memory loads and stores,
and the only way to force it to follow the requested order is to issue
an `eieio' or a `sync' instruction between the instructions that must
be executed 'before' and the ones that must come 'after'.