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Re: Incrementing volatiles?
- To: jvickers at dial dot pipex dot com (John Vickers)
- Subject: Re: Incrementing volatiles?
- From: "Philippe De Muyter" <phdm at macqel dot be>
- Date: Mon, 13 Jul 1998 11:36:32 +0200 (CEST)
- Cc: schwab at issan dot informatik dot uni-dortmund dot de, smurf at noris dot de, egcs at cygnus dot com
Sorry to be slightly off-topic, but this discussion reminds me a problem
I encountered some months ago when writing a driver for a VME board in
an AIX powerpc environment. Although I had declared all the registers
of the chips on the board as volatile, and compiled my driver with gcc,
I saw with a logic analyser on the VME bus that the accesses to the
register on the board were not done in the order I had written them.
To solve that problem, I had to manually add asm("eieio") after each
access to a volatile register. Should gcc not do that for me ?
eieio stands for "Enforce In-Order Execution of I/O". Without it a powerpc
processor assumes that it may reorder the load and stores to memory-mapped
I/O registers.