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Re: {PATCH v3, rs6000] Replace X-form addressing with D-form addressing in new pass for Power9
On 10/17/19 5:57 PM, Segher Boessenkool wrote:
> Hi Kelvin,
>
> On Wed, Oct 09, 2019 at 03:28:45PM -0500, Kelvin Nilsen wrote:
>> This new pass scans existing rtl expressions and replaces them with rtl expressions that favor selection of the D-form instructions in contexts for which the D-form instructions are preferred. The new pass runs after the RTL loop optimizations since loop unrolling often introduces opportunities for beneficial replacements of X-form addressing instructions.
>>
>> For each of the new tests, multiple X-form instructions are replaced with D-form instructions, some addi instructions are replaced with add instructions, and some addi instructions are eliminated. The typical improvement for the included tests is a decrease of 4.28% to 12.12% in the number of instructions executed on each iteration of the loop. The optimization has not shown measurable improvement on specmark tests, presumably because the typical loops that are benefited by this optimization are memory bounded and this optimization does not eliminate memory loads or stores. However, it is anticipated that multi-threaded workloads and measurements of total power and cooling costs for heavy server workloads would benefit.
>
> My first question is, why did ivopts choose the suboptimal solution?
> _Did_ it, or did something later mess things up?
>
> This new pass can help us investigate that. It certainly sounds like we
> could do better earlier already.
>
> I think it is a good design to make fixes late in the pass pipeline, *but*
> we should try to make good choices earlier, too -- the "late tweaks" should
> be just that, tweaks; 4%-12% is a bit much.
>
> (It's not that super late here; but still, why does it help so much?)
>
Thanks Segher for looking over my draft patch and providing your comments. When I first began work
on this reported performance problem, I did look at the earlier passes in hopes of identifying a better place to address the poor instruction selection.
It is difficult to know exactly where we want to accomplish the improved code generation. Some of the "earlier" candidate passes are disadvantaged because they are "blind" to instruction costs and do not even have an awareness of which addressing modes are supported by which instructions.
Below, I'm providing some of the earlier pass information for one of the sample programs that motivates this patch. Please feel free to comment. I welcome suggestions as to alternative ways to attack this.
Thanks.
--------------------------------------------
Consider the following program:
extern float opt_value
extern char *opt_desc;
#define M 128
#define N 512
double x [N];
double y [N];
int main (int argc, char *argv []) {
double sacc;
first_dummy ();
for (int j = 0; j < M; j++) {
sacc = 0.00;
for (unsigned long long int i = 0; i < N; i++)
sacc += x[i] * y[i];
dummy (sacc, N);
}
opt_value = ((float) N) * 2 * ((float) M);
opt_desc = "flops";
other_dummy ();
}
Compile this with the following command-line options on a Power target:
xgcc p9-dform-0.c -da -m64 -fdump-tree-all -fno-diagnostics-show-caret \
-fno-diagnostics-show-line-numbers -fdiagnostics-color=never -O3 \
-mcpu=power9 -mtune=power9 -funroll-loops -ffat-lto-objects -fno-ident
*********************************
* Auto-vectorization transforms this program into approximately the
* following C code
*********************************
int main (int argc, char *argv []) {
double sacc;
vector double x_values, y_values, xy_product;
vector double *vectp_x, *vectp_y;
first_dummy ();
for (int j = 0; j < M; j++) {
sacc = 0.00;
vectp_x = x;
vectp_y = y;
for (unsigned int ivtmp_31 = 0; ivtmp_31 != N / 2; ivtmp_31++) {
x_values = *vectp_x;
y_values = *vectp_y;
xy_product = x_values * y_values;
sacc += xy_product[0];
sacc += xy_product[1];
vectp_x++;
vectp_y++;
}
dummy (sacc, N);
}
opt_value = ((float) N) * 2 * ((float) M);
opt_desc = "flops";
other_dummy ();
}
*********************************
* Induction variable optimization transforms this program into approximately
* the following C code
*********************************
int main (int argc, char *argv []) {
double sacc;
vector double x_values, y_values, xy_product;
first_dummy ();
for (int j = 0; j < M; j++) {
sacc = 0.00;
for (unsigned int ivtmp_14 = 0; ivtmp_31 != 4096; ivtmp_14 += 16) {
x_values = x [ivtmp_14];
y_values = y [ivtmp_14];
xy_product = x_values * y_values;
sacc += xy_product[0];
sacc += xy_product[1];
/* Note: induction variable optimization has removed 2 pointer
* increments of the form "vectp_x++" at the "cost" of replacing
* two direct memory fetches of the form "*vectp_x" with indexed
* memory fetches of the form "x[i]". Since most popular
* architectures support no-cost indexed load instructions, and
* the induction-variable optimization pass does not have
* specific information about instruction costs, it's "difficult"
* to fault its choices here... What might be a good induction
* variable choice on one target may not be so good on a
* different target. */
}
dummy (sacc, N);
}
opt_value = ((float) N) * 2 * ((float) M);
opt_desc = "flops";
other_dummy ();
}
*********************************
* Loop unrolling turns this code into the following:
*********************************
int main (int argc, char *argv []) {
double sacc;
vector double x_values, y_values, xy_product;
vector double *vectp_x, *vectp_y;
bb2:
first_dummy ();
ivtmp_28 = 128;
sacc = 0.00; // reg:DF 146
vectp_y = y; // vectp_y is reg_di_145
vectp_x = x; // vectp_x is reg_di_144
reg_df_146 = 0.0D;
goto bb5;
bb7:
bb5: // Top of outer loop (from bb2 and bb4 via bb7)
// prepare/initialize for the inner loop
ivtmp_14 = 0;
sacc = reg_df_146;
goto bb3
bb3: // Top of inner loop (bb23 iterates to here)
// Unroll 1
y_values = vectp_y [ivtmp_14];
x_values = vectp_x [ivtmp_14];
xy_product = x_values * y_values;
sacc += xy_product[0];
sacc += xy_product[1];
ivtmp_14_base = ivtmp_14 + 16;
ivtmp_14 = ivtmp_14_base;
cr_135 = (ivtmp_14 >= 4096); // apparently dead code
goto bb8;
bb8: // out of order
goto bb10
bb10: // loop body, comes from bb8
// Unroll 2
y_values = vectp_y [ivtmp_14];
x_values = vectp_x [ivtmp_14];
xy_product = x_values * y_values;
sacc += xy_product[0];
sacc += xy_product[1];
ivtmp_14 = ivtmp_14_base + 16;
cr_135 = (ivtmp_14 >= 4096); // apparently dead code, to be removed
goto bb11
bb11:
goto bb12
bb12:
// Unroll 3
y_values = vectp_y [ivtmp_14];
x_values = vectp_x [ivtmp_14];
xy_product = x_values * y_values;
sacc += xy_product[0];
sacc += xy_product[1];
ivtmp_14 = ivtmp_14_base + 32;
cr_135 = (ivtmp_14 >= 4096); // apparently dead code, to be removed
goto bb13
bb13:
goto bb14
bb14:
// Unroll 4
y_values = vectp_y [ivtmp_14];
x_values = vectp_x [ivtmp_14];
xy_product = x_values * y_values;
sacc += xy_product[0];
sacc += xy_product[1];
ivtmp_14 = ivtmp_14_base + 48;
cr_135 = (ivtmp_14 >= 4096); // apparently dead code, to be removed
goto bb15
bb15:
goto bb16
bb16:
// Unroll 5
y_values = vectp_y [ivtmp_14];
x_values = vectp_x [ivtmp_14];
xy_product = x_values * y_values;
sacc += xy_product[0];
sacc += xy_product[1];
ivtmp_14 = ivtmp_14_base + 64;
cr_135 = (ivtmp_14 >= 4096); // apparently dead code, to be removed
goto bb17
bb17:
goto bb18
bb18:
// Unroll 6
y_values = vectp_y [ivtmp_14];
x_values = vectp_x [ivtmp_14];
xy_product = x_values * y_values;
sacc += xy_product[0];
sacc += xy_product[1];
ivtmp_14 = ivtmp_14_base + 80;
cr_135 = (ivtmp_14 >= 4096); // apparently dead code, to be removed
goto bb19
bb19:
goto bb20
bb20:
// Unroll 7
y_values = vectp_y [ivtmp_14];
x_values = vectp_x [ivtmp_14];
xy_product = x_values * y_values;
sacc += xy_product[0];
sacc += xy_product[1];
ivtmp_14 = ivtmp_14_base + 96;
cr_135 = (ivtmp_14 >= 4096); // apparently dead code, to be removed
goto bb21
bb21:
goto bb22
bb22:
// Unroll 8
y_values = vectp_y [ivtmp_14];
x_values = vectp_x [ivtmp_14];
xy_product = x_values * y_values;
sacc += xy_product[0];
sacc += xy_product[1];
ivtmp_14 = ivtmp_14_base + 112;
if (ivtmp_14 == 4096)
goto bb9 // exit the inner loop
else
goto bb23 // continue the inner loop
bb23:
goto bb3
bb9: // outside inner loop, bottom of outer loop
goto bb4
bb4:
dummy (sacc, N);
ivtmp_28 -= 1;
if (ivtmp_28 == 0)
goto bb6 // break out of outer loop
else
goto bb7 // continue the outer loop
bb6: // end this function
opt_value = ((float) N) * 2 * ((float) M);
opt_desc = "flops";
other_dummy ();
goto EXIT
}
Attachments:
******************************************
* p9-dform-0.c (original source)
******************************************
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
/* { dg-skip-if "" { powerpc*-*-aix* } } */
/* { dg-options "-O3 -mcpu=power9 -mtune=power9 -funroll-loops" } */
/* This test confirms that the dform instructions are selected in the
translation of this main program. */
extern void first_dummy ();
extern void dummy (double sacc, int n);
extern void other_dummy ();
extern float opt_value;
extern char *opt_desc;
#define M 128
#define N 512
double x [N];
double y [N];
int main (int argc, char *argv []) {
double sacc;
first_dummy ();
for (int j = 0; j < M; j++) {
sacc = 0.00;
for (unsigned long long int i = 0; i < N; i++) {
sacc += x[i] * y[i];
}
dummy (sacc, N);
}
opt_value = ((float) N) * 2 * ((float) M);
opt_desc = "flops";
other_dummy ();
}
/* At time the dform optimization pass was merged with trunk, 12
lxv instructions were emitted in place of the same number of lxvx
instructions. No need to require exactly this number, as it may
change when other optimization passes evolve. */
/* { dg-final { scan-assembler {\mlxv\M} } } */
******************************************
* p9-dform-0.c.162t.slp1 (auto-vectorization)
******************************************
;; Function main (main, funcdef_no=0, decl_uid=2861, cgraph_uid=1, symbol_order=2) (executed once)
main (int argc, char * * argv)
{
double stmp_sacc_16.10;
vector(2) double vect__3.9;
vector(2) double vect__2.8;
vector(2) double * vectp_y.7;
vector(2) double * vectp_y.6;
vector(2) double vect__1.5;
vector(2) double * vectp_x.4;
vector(2) double * vectp_x.3;
long long unsigned int i;
int j;
double sacc;
unsigned int ivtmp_28;
long long unsigned int ivtmp_29;
long long unsigned int ivtmp_30;
unsigned int ivtmp_31;
<bb 2> [local count: 108459]:
first_dummy ();
goto <bb 5>; [100.00%]
<bb 8> [local count: 526133483]:
<bb 3> [local count: 536870902]:
# sacc_24 = PHI <sacc_16(8), 0.0(5)>
# vectp_x.3_23 = PHI <vectp_x.3_22(8), &x(5)>
# vectp_y.6_20 = PHI <vectp_y.6_19(8), &y(5)>
# ivtmp_30 = PHI <ivtmp_29(8), 0(5)>
vect__1.5_21 = MEM <vector(2) double> [(double *)vectp_x.3_23];
vect__2.8_18 = MEM <vector(2) double> [(double *)vectp_y.6_20];
vect__3.9_10 = vect__1.5_21 * vect__2.8_18;
stmp_sacc_16.10_7 = BIT_FIELD_REF <vect__3.9_10, 64, 0>;
stmp_sacc_16.10_6 = sacc_24 + stmp_sacc_16.10_7;
stmp_sacc_16.10_5 = BIT_FIELD_REF <vect__3.9_10, 64, 64>;
sacc_16 = stmp_sacc_16.10_6 + stmp_sacc_16.10_5;
vectp_x.3_22 = vectp_x.3_23 + 16;
vectp_y.6_19 = vectp_y.6_20 + 16;
ivtmp_29 = ivtmp_30 + 1;
if (ivtmp_29 < 256)
goto <bb 8>; [98.00%]
else
goto <bb 4>; [2.00%]
<bb 4> [local count: 10737418]:
# sacc_34 = PHI <sacc_16(3)>
dummy (sacc_34, 512);
ivtmp_28 = ivtmp_31 - 1;
if (ivtmp_28 != 0)
goto <bb 7>; [98.99%]
else
goto <bb 6>; [1.01%]
<bb 7> [local count: 10628959]:
<bb 5> [local count: 10737418]:
# ivtmp_31 = PHI <128(2), ivtmp_28(7)>
goto <bb 3>; [100.00%]
<bb 6> [local count: 108459]:
opt_value = 1.31072e+5;
opt_desc = "flops";
other_dummy ();
return 0;
}
******************************************
* p9-dform-0.c.164t.ivopts (induction variable optimizations)
******************************************
;; Function main (main, funcdef_no=0, decl_uid=2861, cgraph_uid=1, symbol_order=2) (executed once)
main (int argc, char * * argv)
{
sizetype ivtmp.14;
double stmp_sacc_16.10;
vector(2) double vect__3.9;
vector(2) double vect__2.8;
vector(2) double * vectp_y.7;
vector(2) double * vectp_y.6;
vector(2) double vect__1.5;
vector(2) double * vectp_x.4;
vector(2) double * vectp_x.3;
long long unsigned int i;
int j;
double sacc;
unsigned int ivtmp_28;
unsigned int ivtmp_31;
<bb 2> [local count: 108459]:
first_dummy ();
goto <bb 5>; [100.00%]
<bb 8> [local count: 526133483]:
<bb 3> [local count: 536870902]:
# sacc_24 = PHI <sacc_16(8), 0.0(5)>
# ivtmp.14_25 = PHI <ivtmp.14_33(8), 0(5)>
vect__1.5_21 = MEM[symbol: x, index: ivtmp.14_25, offset: 0B];
vect__2.8_18 = MEM[symbol: y, index: ivtmp.14_25, offset: 0B];
vect__3.9_10 = vect__1.5_21 * vect__2.8_18;
stmp_sacc_16.10_7 = BIT_FIELD_REF <vect__3.9_10, 64, 0>;
stmp_sacc_16.10_6 = sacc_24 + stmp_sacc_16.10_7;
stmp_sacc_16.10_5 = BIT_FIELD_REF <vect__3.9_10, 64, 64>;
sacc_16 = stmp_sacc_16.10_6 + stmp_sacc_16.10_5;
ivtmp.14_33 = ivtmp.14_25 + 16;
if (ivtmp.14_33 != 4096)
goto <bb 8>; [98.00%]
else
goto <bb 4>; [2.00%]
<bb 4> [local count: 10737418]:
# sacc_34 = PHI <sacc_16(3)>
dummy (sacc_34, 512);
ivtmp_28 = ivtmp_31 - 1;
if (ivtmp_28 != 0)
goto <bb 7>; [98.99%]
else
goto <bb 6>; [1.01%]
<bb 7> [local count: 10628959]:
<bb 5> [local count: 10737418]:
# ivtmp_31 = PHI <128(2), ivtmp_28(7)>
goto <bb 3>; [100.00%]
<bb 6> [local count: 108459]:
opt_value = 1.31072e+5;
opt_desc = "flops";
other_dummy ();
return 0;
}
******************************************
* p9-dform-0.c.253r.loop2_unroll (after vectorized inner loop unrolled 8 times)
******************************************
;; Function main (main, funcdef_no=0, decl_uid=2861, cgraph_uid=1, symbol_order=2) (executed once)
main
Dataflow summary:
;; invalidated by call 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr]
;; hardware regs used 1 [1] 2 [2] 99 [ap] 109 [vscr] 110 [sfp]
;; regular block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; eh block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; entry block defs 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; exit block uses 1 [1] 2 [2] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; regs ever live 1 [1] 2 [2] 3 [3] 4 [4] 33 [1] 96 [lr] 109 [vscr]
;; ref usage r0={3d} r1={1d,11u} r2={1d,17u} r3={5d,2u} r4={5d,1u} r5={4d} r6={4d} r7={4d} r8={4d} r9={4d} r10={4d} r11={3d} r12={3d} r13={3d} r31={1d,8u} r32={3d} r33={5d,1u} r34={4d} r35={4d} r36={4d} r37={4d} r38={4d} r39={4d} r40={4d} r41={4d} r42={4d} r43={4d} r44={4d} r45={4d} r64={3d} r65={3d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={3d} r79={3d} r80={3d} r81={3d} r82={3d} r83={3d} r96={4d} r97={3d} r98={3d} r99={1d,7u} r100={3d} r101={3d} r105={3d} r106={3d} r107={3d} r108={1u} r109={4d,4u} r110={1d,8u} r119={1d,1u} r120={1d,1u} r121={1d,2u} r122={2d,2u} r125={2d,4u,2e} r126={2d,2u} r131={1d,1u} r133={1d,1u} r134={1d,1u} r135={1d,1u} r136={1d,1u} r137={1d,1u} r138={1d,1u} r140={1d,1u} r141={1d,1u} r142={1d,1u} r144={1d,1u} r145={1d,1u} r146={1d,1u}
;; total ref usage 317{230d,85u,2e} in 33{30 regular + 3 call} insns.
( )->[0]->( 2 )
;; bb 0 artificial_defs: { d-1(1){ }d-1(2){ }d-1(3){ }d-1(4){ }d-1(5){ }d-1(6){ }d-1(7){ }d-1(8){ }d-1(9){ }d-1(10){ }d-1(31){ }d-1(33){ }d-1(34){ }d-1(35){ }d-1(36){ }d-1(37){ }d-1(38){ }d-1(39){ }d-1(40){ }d-1(41){ }d-1(42){ }d-1(43){ }d-1(44){ }d-1(45){ }d-1(66){ }d-1(67){ }d-1(68){ }d-1(69){ }d-1(70){ }d-1(71){ }d-1(72){ }d-1(73){ }d-1(74){ }d-1(75){ }d-1(76){ }d-1(77){ }d-1(96){ }d-1(99){ }d-1(109){ }d-1(110){ }}
;; bb 0 artificial_uses: { }
;; lr in 108 [vrsave]
;; lr use
;; lr def 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; live in
;; live gen 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; live kill
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
( 0 )->[2]->( 5 )
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(1){ }u1(2){ }u2(31){ }u3(99){ }u4(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; lr def 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] 126 144 145
;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; live gen 109 [vscr] 126 144 145
;; live kill 96 [lr]
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 126 144 145
;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145
( 5 8 )->[3]->( 8 4 )
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u8(1){ }u9(2){ }u10(31){ }u11(99){ }u12(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 122 125 144 145
;; lr def 119 120 121 122 125 131 133 134 135
;; live in 109 [vscr] 122 125 126
;; live gen 119 120 121 122 125 131 133 134 135
;; live kill
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145
;; live out 109 [vscr] 122 125 126
( 3 )->[8]->( 3 )
;; bb 8 artificial_defs: { }
;; bb 8 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; lr def
;; live in 109 [vscr] 122 125 126
;; live gen
;; live kill
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145
;; live out 109 [vscr] 122 125 126
( 3 )->[4]->( 7 6 )
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u30(1){ }u31(2){ }u32(31){ }u33(99){ }u34(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 126 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 126
;; lr def 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] 126 136 137
;; live in 109 [vscr] 122 126
;; live gen 4 [4] 33 [1] 109 [vscr] 126 136 137
;; live kill 96 [lr]
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145
;; live out 109 [vscr] 126
( 4 )->[7]->( 5 )
;; bb 7 artificial_defs: { }
;; bb 7 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; lr def
;; live in 109 [vscr] 126
;; live gen
;; live kill
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145
;; live out 109 [vscr] 126
( 2 7 )->[5]->( 3 )
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u45(1){ }u46(2){ }u47(31){ }u48(99){ }u49(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; lr def 122 125
;; live in 109 [vscr] 126
;; live gen 122 125
;; live kill
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145
;; live out 109 [vscr] 122 125 126
( 4 )->[6]->( 1 )
;; bb 6 artificial_defs: { }
;; bb 6 artificial_uses: { u50(1){ }u51(2){ }u52(31){ }u53(99){ }u54(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; lr def 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] 138 140 141 142
;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; live gen 3 [3] 109 [vscr] 138 140 141 142
;; live kill 96 [lr]
;; lr out 1 [1] 2 [2] 3 [3] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; live out 1 [1] 2 [2] 3 [3] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
( 6 )->[1]->( )
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u68(1){ }u69(2){ }u70(3){ }u71(31){ }u72(108){ }u73(109){ }u74(110){ }}
;; lr in 1 [1] 2 [2] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; lr use 1 [1] 2 [2] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; lr def
;; live in 1 [1] 2 [2] 3 [3] 31 [31] 109 [vscr] 110 [sfp]
;; live gen
;; live kill
;; lr out
;; live out
starting the processing of deferred insns
ending the processing of deferred insns
setting blocks to analyze 3, 8
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 9 n_edges 10 count 3 ( 0.33)
df_worklist_dataflow_doublequeue: n_basic_blocks 9 n_edges 10 count 2 ( 0.22)
df_worklist_dataflow_doublequeue: n_basic_blocks 9 n_edges 10 count 3 ( 0.33)
starting region dump
main
Dataflow summary:
def_info->table_size = 9, use_info->table_size = 76
;; invalidated by call 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr]
;; hardware regs used 1 [1] 2 [2] 99 [ap] 109 [vscr] 110 [sfp]
;; regular block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; eh block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; entry block defs 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; exit block uses 1 [1] 2 [2] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; regs ever live 1 [1] 2 [2] 3 [3] 4 [4] 33 [1] 96 [lr] 109 [vscr]
;; ref usage r0={3d} r1={1d,11u} r2={1d,17u} r3={5d,2u} r4={5d,1u} r5={4d} r6={4d} r7={4d} r8={4d} r9={4d} r10={4d} r11={3d} r12={3d} r13={3d} r31={1d,8u} r32={3d} r33={5d,1u} r34={4d} r35={4d} r36={4d} r37={4d} r38={4d} r39={4d} r40={4d} r41={4d} r42={4d} r43={4d} r44={4d} r45={4d} r64={3d} r65={3d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={3d} r79={3d} r80={3d} r81={3d} r82={3d} r83={3d} r96={4d} r97={3d} r98={3d} r99={1d,7u} r100={3d} r101={3d} r105={3d} r106={3d} r107={3d} r108={1u} r109={4d,4u} r110={1d,8u} r119={1d,1u} r120={1d,1u} r121={1d,2u} r122={2d,2u} r125={2d,4u,2e} r126={2d,2u} r131={1d,1u} r133={1d,1u} r134={1d,1u} r135={1d,1u} r136={1d,1u} r137={1d,1u} r138={1d,1u} r140={1d,1u} r141={1d,1u} r142={1d,1u} r144={1d,1u} r145={1d,1u} r146={1d,1u}
;; total ref usage 317{230d,85u,2e} in 33{30 regular + 3 call} insns.
;; Reaching defs:
;; sparse invalidated
;; dense invalidated
;; reg->defs[] map: 119[0,0] 120[1,1] 121[2,2] 122[3,3] 125[4,4] 131[5,5] 133[6,6] 134[7,7] 135[8,8]
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u8(1){ }u9(2){ }u10(31){ }u11(99){ }u12(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 122 125 144 145
;; lr def 119 120 121 122 125 131 133 134 135
;; live in 122 125
;; live gen 119 120 121 122 125 131 133 134 135
;; live kill
;; rd in (2) 122[3],125[4]
;; rd gen (9) 119[0],120[1],121[2],122[3],125[4],131[5],133[6],134[7],135[8]
;; rd kill (9) 119[0],120[1],121[2],122[3],125[4],131[5],133[6],134[7],135[8]
;; UD chains for artificial uses at top
(code_label 24 6 13 3 3 (nil) [0 uses])
(note 13 24 15 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
;; UD chains for insn luid 0 uid 15
;; reg 125 { d4(bb 3 insn 23) }
;; reg 145 { }
;; eq_note reg 125 { d4(bb 3 insn 23) }
(insn 15 13 17 3 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(expr_list:REG_EQUAL (mem:V2DF (plus:DI (reg:DI 125 [ ivtmp.14 ])
(symbol_ref:DI ("y") [flags 0x80] <var_decl 0x3fff88d405a0 y>)) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])
(nil))))
;; UD chains for insn luid 1 uid 17
;; reg 125 { d4(bb 3 insn 23) }
;; reg 144 { }
;; eq_note reg 125 { d4(bb 3 insn 23) }
(insn 17 15 18 3 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(expr_list:REG_EQUAL (mem:V2DF (plus:DI (reg:DI 125 [ ivtmp.14 ])
(symbol_ref:DI ("x") [flags 0x80] <var_decl 0x3fff88d40510 x>)) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])
(nil))))
;; UD chains for insn luid 2 uid 18
;; reg 131 { d5(bb 3 insn 15) }
;; reg 133 { d6(bb 3 insn 17) }
(insn 18 17 19 3 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
;; UD chains for insn luid 3 uid 19
;; reg 121 { d2(bb 3 insn 18) }
(insn 19 18 20 3 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
;; UD chains for insn luid 4 uid 20
;; reg 120 { d1(bb 3 insn 19) }
;; reg 122 { d3(bb 3 insn 22) }
(insn 20 19 21 3 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
;; UD chains for insn luid 5 uid 21
;; reg 121 { d2(bb 3 insn 18) }
(insn 21 20 22 3 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
;; UD chains for insn luid 6 uid 22
;; reg 119 { d0(bb 3 insn 20) }
;; reg 134 { d7(bb 3 insn 21) }
(insn 22 21 23 3 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
;; UD chains for insn luid 7 uid 23
;; reg 125 { d4(bb 3 insn 23) }
(insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
;; UD chains for insn luid 8 uid 25
;; reg 125 { d4(bb 3 insn 23) }
(insn 25 23 26 3 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
;; UD chains for insn luid 9 uid 26
;; reg 135 { d8(bb 3 insn 25) }
(jump_insn 26 25 67 3 (set (pc)
(if_then_else (ne (reg:CCUNS 135)
(const_int 0 [0]))
(label_ref:DI 67)
(pc))) 794 {*cbranch}
(expr_list:REG_DEAD (reg:CCUNS 135)
(int_list:REG_BR_PROB 1052266990 (nil)))
-> 67)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; live out 122 125
;; rd out (2) 122[3],125[4]
;; UD chains for artificial uses at bottom
;; reg 1 { }
;; reg 2 { }
;; reg 31 { }
;; reg 99 { }
;; reg 110 { }
;; bb 8 artificial_defs: { }
;; bb 8 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; lr def
;; live in 122 125
;; live gen
;; live kill
;; rd in (9) 119[0],120[1],121[2],122[3],125[4],131[5],133[6],134[7],135[8]
;; rd gen (0)
;; rd kill (0)
;; UD chains for artificial uses at top
(code_label 67 26 66 8 5 (nil) [1 uses])
(note 66 67 27 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; live out 122 125
;; rd out (2) 122[3],125[4]
;; UD chains for artificial uses at bottom
;; reg 1 { }
;; reg 2 { }
;; reg 31 { }
;; reg 99 { }
;; reg 110 { }
Analyzing operand (reg:DI 125 [ ivtmp.14 ]) of insn (insn 25 23 26 3 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
Analyzing def of (reg:DI 125 [ ivtmp.14 ]) in insn (insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
Analyzing operand (reg:DI 125 [ ivtmp.14 ]) of insn (insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
Analyzing (reg:DI 125 [ ivtmp.14 ]) for bivness.
(reg:DI 125 [ ivtmp.14 ]) + (const_int 16 [0x10]) * iteration (in DI)
Analyzing operand (const_int 16 [0x10]) of insn (insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
invariant (const_int 16 [0x10]) (in DI)
(reg:DI 125 [ ivtmp.14 ]) in insn (insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
is (plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10])) + (const_int 16 [0x10]) * iteration (in DI)
Analyzing operand (const_int 4096 [0x1000]) of insn (insn 25 23 26 3 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
invariant (const_int 4096 [0x1000]) (in DI)
Loop 2 is simple:
simple exit 3 -> 4
number of iterations: (const_int 255 [0xff])
upper bound: 255
likely upper bound: 255
realistic bound: 255
starting the processing of deferred insns
ending the processing of deferred insns
setting blocks to analyze 3, 4, 5, 7, 8
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 9 n_edges 10 count 9 ( 1)
df_worklist_dataflow_doublequeue: n_basic_blocks 9 n_edges 10 count 9 ( 1)
df_worklist_dataflow_doublequeue: n_basic_blocks 9 n_edges 10 count 11 ( 1.2)
starting region dump
main
Dataflow summary:
def_info->table_size = 71, use_info->table_size = 76
;; invalidated by call 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr]
;; hardware regs used 1 [1] 2 [2] 99 [ap] 109 [vscr] 110 [sfp]
;; regular block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; eh block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; entry block defs 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; exit block uses 1 [1] 2 [2] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; regs ever live 1 [1] 2 [2] 3 [3] 4 [4] 33 [1] 96 [lr] 109 [vscr]
;; ref usage r0={3d} r1={1d,11u} r2={1d,17u} r3={5d,2u} r4={5d,1u} r5={4d} r6={4d} r7={4d} r8={4d} r9={4d} r10={4d} r11={3d} r12={3d} r13={3d} r31={1d,8u} r32={3d} r33={5d,1u} r34={4d} r35={4d} r36={4d} r37={4d} r38={4d} r39={4d} r40={4d} r41={4d} r42={4d} r43={4d} r44={4d} r45={4d} r64={3d} r65={3d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={3d} r79={3d} r80={3d} r81={3d} r82={3d} r83={3d} r96={4d} r97={3d} r98={3d} r99={1d,7u} r100={3d} r101={3d} r105={3d} r106={3d} r107={3d} r108={1u} r109={4d,4u} r110={1d,8u} r119={1d,1u} r120={1d,1u} r121={1d,2u} r122={2d,2u} r125={2d,4u,2e} r126={2d,2u} r131={1d,1u} r133={1d,1u} r134={1d,1u} r135={1d,1u} r136={1d,1u} r137={1d,1u} r138={1d,1u} r140={1d,1u} r141={1d,1u} r142={1d,1u} r144={1d,1u} r145={1d,1u} r146={1d,1u}
;; total ref usage 317{230d,85u,2e} in 33{30 regular + 3 call} insns.
;; Reaching defs:
;; sparse invalidated
;; dense invalidated 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56
;; reg->defs[] map: 0[0,0] 3[1,1] 4[2,3] 5[4,4] 6[5,5] 7[6,6] 8[7,7] 9[8,8] 10[9,9] 11[10,10] 12[11,11] 13[12,12] 32[13,13] 33[14,15] 34[16,16] 35[17,17] 36[18,18] 37[19,19] 38[20,20] 39[21,21] 40[22,22] 41[23,23] 42[24,24] 43[25,25] 44[26,26] 45[27,27] 64[28,28] 65[29,29] 66[30,30] 67[31,31] 68[32,32] 69[33,33] 70[34,34] 71[35,35] 72[36,36] 73[37,37] 74[38,38] 75[39,39] 76[40,40] 77[41,41] 78[42,42] 79[43,43] 80[44,44] 81[45,45] 82[46,46] 83[47,47] 96[48,48] 97[49,49] 98[50,50] 100[51,51] 101[52,52] 105[53,53] 106[54,54] 107[55,55] 109[56,56] 119[57,57] 120[58,58] 121[59,59] 122[60,61] 125[62,63] 126[64,64] 131[65,65] 133[66,66] 134[67,67] 135[68,68] 136[69,69] 137[70,70]
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u8(1){ }u9(2){ }u10(31){ }u11(99){ }u12(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145 146
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 122 125 144 145
;; lr def 119 120 121 122 125 131 133 134 135
;; live in 109 [vscr] 122 125 126
;; live gen 119 120 121 122 125 131 133 134 135
;; live kill
;; rd in (6) 109[56],122[60,61],125[62,63],126[64]
;; rd gen (9) 119[57],120[58],121[59],122[60],125[62],131[65],133[66],134[67],135[68]
;; rd kill (11) 119[57],120[58],121[59],122[60,61],125[62,63],131[65],133[66],134[67],135[68]
;; UD chains for artificial uses at top
(code_label 24 6 13 3 3 (nil) [0 uses])
(note 13 24 15 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
;; UD chains for insn luid 0 uid 15
;; reg 125 { d63(bb 5 insn 5) d62(bb 3 insn 23) }
;; reg 145 { }
;; eq_note reg 125 { d63(bb 5 insn 5) d62(bb 3 insn 23) }
(insn 15 13 17 3 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(expr_list:REG_EQUAL (mem:V2DF (plus:DI (reg:DI 125 [ ivtmp.14 ])
(symbol_ref:DI ("y") [flags 0x80] <var_decl 0x3fff88d405a0 y>)) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])
(nil))))
;; UD chains for insn luid 1 uid 17
;; reg 125 { d63(bb 5 insn 5) d62(bb 3 insn 23) }
;; reg 144 { }
;; eq_note reg 125 { d63(bb 5 insn 5) d62(bb 3 insn 23) }
(insn 17 15 18 3 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(expr_list:REG_EQUAL (mem:V2DF (plus:DI (reg:DI 125 [ ivtmp.14 ])
(symbol_ref:DI ("x") [flags 0x80] <var_decl 0x3fff88d40510 x>)) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])
(nil))))
;; UD chains for insn luid 2 uid 18
;; reg 131 { d65(bb 3 insn 15) }
;; reg 133 { d66(bb 3 insn 17) }
(insn 18 17 19 3 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
;; UD chains for insn luid 3 uid 19
;; reg 121 { d59(bb 3 insn 18) }
(insn 19 18 20 3 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
;; UD chains for insn luid 4 uid 20
;; reg 120 { d58(bb 3 insn 19) }
;; reg 122 { d61(bb 5 insn 68) d60(bb 3 insn 22) }
(insn 20 19 21 3 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
;; UD chains for insn luid 5 uid 21
;; reg 121 { d59(bb 3 insn 18) }
(insn 21 20 22 3 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
;; UD chains for insn luid 6 uid 22
;; reg 119 { d57(bb 3 insn 20) }
;; reg 134 { d67(bb 3 insn 21) }
(insn 22 21 23 3 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
;; UD chains for insn luid 7 uid 23
;; reg 125 { d63(bb 5 insn 5) d62(bb 3 insn 23) }
(insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
;; UD chains for insn luid 8 uid 25
;; reg 125 { d62(bb 3 insn 23) }
(insn 25 23 26 3 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
;; UD chains for insn luid 9 uid 26
;; reg 135 { d68(bb 3 insn 25) }
(jump_insn 26 25 67 3 (set (pc)
(if_then_else (ne (reg:CCUNS 135)
(const_int 0 [0]))
(label_ref:DI 67)
(pc))) 794 {*cbranch}
(expr_list:REG_DEAD (reg:CCUNS 135)
(int_list:REG_BR_PROB 1052266990 (nil)))
-> 67)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145 146
;; live out 109 [vscr] 122 125 126
;; rd out (4) 109[56],122[60],125[62],126[64]
;; UD chains for artificial uses at bottom
;; reg 1 { }
;; reg 2 { }
;; reg 31 { }
;; reg 99 { }
;; reg 110 { }
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u30(1){ }u31(2){ }u32(31){ }u33(99){ }u34(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 126 144 145 146
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 126
;; lr def 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] 126 136 137
;; live in 109 [vscr] 122 126
;; live gen 4 [4] 33 [1] 109 [vscr] 126 136 137
;; live kill 96 [lr]
;; rd in (4) 109[56],122[60],125[62],126[64]
;; rd gen (4) 109[56],126[64],136[69],137[70]
;; rd kill (5) 96[48],109[56],126[64],136[69],137[70]
;; UD chains for artificial uses at top
(note 27 66 28 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
;; UD chains for insn luid 0 uid 28
(insn 28 27 29 4 (set (reg:DI 4 4)
(const_int 512 [0x200])) "p9-dform-0.c":33:5 609 {*movdi_internal64}
(nil))
;; UD chains for insn luid 1 uid 29
;; reg 122 { d60(bb 3 insn 22) }
(insn 29 28 30 4 (set (reg:DF 33 1)
(reg/v:DF 122 [ sacc ])) "p9-dform-0.c":33:5 512 {*movdf_hardfloat64}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(nil)))
;; UD chains for insn luid 2 uid 30
;; reg 1 { }
;; reg 109 { d56(bb 4 insn 30) }
;; reg 2 { }
;; reg 4 { d2(bb 4 insn 28) }
;; reg 33 { d14(bb 4 insn 29) }
(call_insn 30 29 31 4 (parallel [
(call (mem:SI (symbol_ref:DI ("dummy") [flags 0x41] <function_decl 0x3fff863be100 dummy>) [0 dummy S4 A8])
(const_int 0 [0]))
(clobber (reg:DI 96 lr))
]) "p9-dform-0.c":33:5 704 {*call_nonlocal_aixdi}
(expr_list:REG_DEAD (reg:DF 33 1)
(expr_list:REG_DEAD (reg:DI 4 4)
(expr_list:REG_CALL_DECL (symbol_ref:DI ("dummy") [flags 0x41] <function_decl 0x3fff863be100 dummy>)
(nil))))
(expr_list (use (reg:DI 2 2))
(expr_list:DF (use (reg:DF 33 1))
(expr_list:SI (use (reg:DI 4 4))
(nil)))))
;; UD chains for insn luid 3 uid 31
;; reg 126 { d64(bb 4 insn 32) }
(insn 31 30 32 4 (set (reg:SI 136)
(plus:SI (subreg/s/v:SI (reg:DI 126 [ ivtmp_28 ]) 0)
(const_int -1 [0xffffffffffffffff]))) "p9-dform-0.c":27:3 68 {*addsi3}
(expr_list:REG_DEAD (reg:DI 126 [ ivtmp_28 ])
(nil)))
;; UD chains for insn luid 4 uid 32
;; reg 136 { d69(bb 4 insn 31) }
(insn 32 31 33 4 (set (reg:DI 126 [ ivtmp_28 ])
(zero_extend:DI (reg:SI 136))) "p9-dform-0.c":27:3 19 {zero_extendsidi2}
(expr_list:REG_DEAD (reg:SI 136)
(nil)))
;; UD chains for insn luid 5 uid 33
;; reg 126 { d64(bb 4 insn 32) }
(insn 33 32 34 4 (set (reg:CC 137)
(compare:CC (reg:DI 126 [ ivtmp_28 ])
(const_int 0 [0]))) "p9-dform-0.c":27:3 730 {*cmpdi_signed}
(nil))
;; UD chains for insn luid 6 uid 34
;; reg 137 { d70(bb 4 insn 33) }
(jump_insn 34 33 65 4 (set (pc)
(if_then_else (eq (reg:CC 137)
(const_int 0 [0]))
(label_ref 39)
(pc))) "p9-dform-0.c":27:3 794 {*cbranch}
(expr_list:REG_DEAD (reg:CC 137)
(int_list:REG_BR_PROB 10845908 (nil)))
-> 39)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145 146
;; live out 109 [vscr] 126
;; rd out (2) 109[56],126[64]
;; UD chains for artificial uses at bottom
;; reg 1 { }
;; reg 2 { }
;; reg 31 { }
;; reg 99 { }
;; reg 110 { }
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u45(1){ }u46(2){ }u47(31){ }u48(99){ }u49(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145 146
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 146
;; lr def 122 125
;; live in 109 [vscr] 126
;; live gen 122 125
;; live kill
;; rd in (2) 109[56],126[64]
;; rd gen (2) 122[61],125[63]
;; rd kill (4) 122[60,61],125[62,63]
;; UD chains for artificial uses at top
(code_label 35 65 36 5 2 (nil) [0 uses])
(note 36 35 5 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
;; UD chains for insn luid 0 uid 5
(insn 5 36 68 5 (set (reg:DI 125 [ ivtmp.14 ])
(const_int 0 [0])) "p9-dform-0.c":23:36 609 {*movdi_internal64}
(nil))
;; UD chains for insn luid 1 uid 68
;; reg 146 { }
(insn 68 5 39 5 (set (reg/v:DF 122 [ sacc ])
(reg:DF 146 [ sacc ])) "p9-dform-0.c":29:10 -1
(expr_list:REG_DEAD (reg:DF 146 [ sacc ])
(nil)))
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145 146
;; live out 109 [vscr] 122 125 126
;; rd out (4) 109[56],122[61],125[63],126[64]
;; UD chains for artificial uses at bottom
;; reg 1 { }
;; reg 2 { }
;; reg 31 { }
;; reg 99 { }
;; reg 110 { }
;; bb 7 artificial_defs: { }
;; bb 7 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145 146
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; lr def
;; live in 109 [vscr] 126
;; live gen
;; live kill
;; rd in (2) 109[56],126[64]
;; rd gen (0)
;; rd kill (0)
;; UD chains for artificial uses at top
(note 65 34 35 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145 146
;; live out 109 [vscr] 126
;; rd out (2) 109[56],126[64]
;; UD chains for artificial uses at bottom
;; reg 1 { }
;; reg 2 { }
;; reg 31 { }
;; reg 99 { }
;; reg 110 { }
;; bb 8 artificial_defs: { }
;; bb 8 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145 146
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; lr def
;; live in 109 [vscr] 122 125 126
;; live gen
;; live kill
;; rd in (11) 109[56],119[57],120[58],121[59],122[60],125[62],126[64],131[65],133[66],134[67],135[68]
;; rd gen (0)
;; rd kill (0)
;; UD chains for artificial uses at top
(code_label 67 26 66 8 5 (nil) [1 uses])
(note 66 67 27 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145 146
;; live out 109 [vscr] 122 125 126
;; rd out (4) 109[56],122[60],125[62],126[64]
;; UD chains for artificial uses at bottom
;; reg 1 { }
;; reg 2 { }
;; reg 31 { }
;; reg 99 { }
;; reg 110 { }
Analyzing operand (reg:DI 126 [ ivtmp_28 ]) of insn (insn 33 32 34 4 (set (reg:CC 137)
(compare:CC (reg:DI 126 [ ivtmp_28 ])
(const_int 0 [0]))) "p9-dform-0.c":27:3 730 {*cmpdi_signed}
(nil))
Analyzing def of (reg:DI 126 [ ivtmp_28 ]) in insn (insn 32 31 33 4 (set (reg:DI 126 [ ivtmp_28 ])
(zero_extend:DI (reg:SI 136))) "p9-dform-0.c":27:3 19 {zero_extendsidi2}
(expr_list:REG_DEAD (reg:SI 136)
(nil)))
Analyzing operand (reg:SI 136) of insn (insn 32 31 33 4 (set (reg:DI 126 [ ivtmp_28 ])
(zero_extend:DI (reg:SI 136))) "p9-dform-0.c":27:3 19 {zero_extendsidi2}
(expr_list:REG_DEAD (reg:SI 136)
(nil)))
Analyzing def of (reg:SI 136) in insn (insn 31 30 32 4 (set (reg:SI 136)
(plus:SI (subreg/s/v:SI (reg:DI 126 [ ivtmp_28 ]) 0)
(const_int -1 [0xffffffffffffffff]))) "p9-dform-0.c":27:3 68 {*addsi3}
(expr_list:REG_DEAD (reg:DI 126 [ ivtmp_28 ])
(nil)))
Analyzing operand (subreg/s/v:SI (reg:DI 126 [ ivtmp_28 ]) 0) of insn (insn 31 30 32 4 (set (reg:SI 136)
(plus:SI (subreg/s/v:SI (reg:DI 126 [ ivtmp_28 ]) 0)
(const_int -1 [0xffffffffffffffff]))) "p9-dform-0.c":27:3 68 {*addsi3}
(expr_list:REG_DEAD (reg:DI 126 [ ivtmp_28 ])
(nil)))
Analyzing operand (reg:DI 126 [ ivtmp_28 ]) of insn (insn 31 30 32 4 (set (reg:SI 136)
(plus:SI (subreg/s/v:SI (reg:DI 126 [ ivtmp_28 ]) 0)
(const_int -1 [0xffffffffffffffff]))) "p9-dform-0.c":27:3 68 {*addsi3}
(expr_list:REG_DEAD (reg:DI 126 [ ivtmp_28 ])
(nil)))
Analyzing (reg:DI 126 [ ivtmp_28 ]) for bivness.
(reg:DI 126 [ ivtmp_28 ]) + (const_int -1 [0xffffffffffffffff]) * iteration (in SI) zero_extend to DI (first special)
Analyzing operand (const_int -1 [0xffffffffffffffff]) of insn (insn 31 30 32 4 (set (reg:SI 136)
(plus:SI (subreg/s/v:SI (reg:DI 126 [ ivtmp_28 ]) 0)
(const_int -1 [0xffffffffffffffff]))) "p9-dform-0.c":27:3 68 {*addsi3}
(expr_list:REG_DEAD (reg:DI 126 [ ivtmp_28 ])
(nil)))
invariant (const_int -1 [0xffffffffffffffff]) (in SI)
(reg:SI 136) in insn (insn 31 30 32 4 (set (reg:SI 136)
(plus:SI (subreg/s/v:SI (reg:DI 126 [ ivtmp_28 ]) 0)
(const_int -1 [0xffffffffffffffff]))) "p9-dform-0.c":27:3 68 {*addsi3}
(expr_list:REG_DEAD (reg:DI 126 [ ivtmp_28 ])
(nil)))
is (plus:DI (reg:DI 126 [ ivtmp_28 ])
(const_int 4294967295 [0xffffffff])) + (const_int -1 [0xffffffffffffffff]) * iteration (in SI) UnKnown to DI
(reg:DI 126 [ ivtmp_28 ]) in insn (insn 32 31 33 4 (set (reg:DI 126 [ ivtmp_28 ])
(zero_extend:DI (reg:SI 136))) "p9-dform-0.c":27:3 19 {zero_extendsidi2}
(expr_list:REG_DEAD (reg:SI 136)
(nil)))
is (plus:DI (reg:DI 126 [ ivtmp_28 ])
(const_int 4294967295 [0xffffffff])) + (const_int -1 [0xffffffffffffffff]) * iteration (in SI) zero_extend to DI
Analyzing operand (const_int 0 [0]) of insn (insn 33 32 34 4 (set (reg:CC 137)
(compare:CC (reg:DI 126 [ ivtmp_28 ])
(const_int 0 [0]))) "p9-dform-0.c":27:3 730 {*cmpdi_signed}
(nil))
invariant (const_int 0 [0]) (in DI)
Loop 1 is simple:
simple exit 4 -> 6
number of iterations: (const_int 127 [0x7f])
upper bound: 127
likely upper bound: 127
realistic bound: 127
;; Not considering loop, is not innermost
starting the processing of deferred insns
ending the processing of deferred insns
setting blocks to analyze 3, 8
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue: n_basic_blocks 9 n_edges 10 count 3 ( 0.33)
df_worklist_dataflow_doublequeue: n_basic_blocks 9 n_edges 10 count 2 ( 0.22)
df_worklist_dataflow_doublequeue: n_basic_blocks 9 n_edges 10 count 3 ( 0.33)
starting region dump
main
Dataflow summary:
def_info->table_size = 9, use_info->table_size = 76
;; invalidated by call 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr]
;; hardware regs used 1 [1] 2 [2] 99 [ap] 109 [vscr] 110 [sfp]
;; regular block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; eh block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; entry block defs 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; exit block uses 1 [1] 2 [2] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; regs ever live 1 [1] 2 [2] 3 [3] 4 [4] 33 [1] 96 [lr] 109 [vscr]
;; ref usage r0={3d} r1={1d,11u} r2={1d,17u} r3={5d,2u} r4={5d,1u} r5={4d} r6={4d} r7={4d} r8={4d} r9={4d} r10={4d} r11={3d} r12={3d} r13={3d} r31={1d,8u} r32={3d} r33={5d,1u} r34={4d} r35={4d} r36={4d} r37={4d} r38={4d} r39={4d} r40={4d} r41={4d} r42={4d} r43={4d} r44={4d} r45={4d} r64={3d} r65={3d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={3d} r79={3d} r80={3d} r81={3d} r82={3d} r83={3d} r96={4d} r97={3d} r98={3d} r99={1d,7u} r100={3d} r101={3d} r105={3d} r106={3d} r107={3d} r108={1u} r109={4d,4u} r110={1d,8u} r119={1d,1u} r120={1d,1u} r121={1d,2u} r122={2d,2u} r125={2d,4u,2e} r126={2d,2u} r131={1d,1u} r133={1d,1u} r134={1d,1u} r135={1d,1u} r136={1d,1u} r137={1d,1u} r138={1d,1u} r140={1d,1u} r141={1d,1u} r142={1d,1u} r144={1d,1u} r145={1d,1u} r146={1d,1u}
;; total ref usage 317{230d,85u,2e} in 33{30 regular + 3 call} insns.
;; Reaching defs:
;; sparse invalidated
;; dense invalidated
;; reg->defs[] map: 119[0,0] 120[1,1] 121[2,2] 122[3,3] 125[4,4] 131[5,5] 133[6,6] 134[7,7] 135[8,8]
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u8(1){ }u9(2){ }u10(31){ }u11(99){ }u12(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 122 125 144 145
;; lr def 119 120 121 122 125 131 133 134 135
;; live in 122 125
;; live gen 119 120 121 122 125 131 133 134 135
;; live kill
;; rd in (2) 122[3],125[4]
;; rd gen (9) 119[0],120[1],121[2],122[3],125[4],131[5],133[6],134[7],135[8]
;; rd kill (9) 119[0],120[1],121[2],122[3],125[4],131[5],133[6],134[7],135[8]
;; UD chains for artificial uses at top
(code_label 24 6 13 3 3 (nil) [0 uses])
(note 13 24 15 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
;; UD chains for insn luid 0 uid 15
;; reg 125 { d4(bb 3 insn 23) }
;; reg 145 { }
;; eq_note reg 125 { d4(bb 3 insn 23) }
(insn 15 13 17 3 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(expr_list:REG_EQUAL (mem:V2DF (plus:DI (reg:DI 125 [ ivtmp.14 ])
(symbol_ref:DI ("y") [flags 0x80] <var_decl 0x3fff88d405a0 y>)) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])
(nil))))
;; UD chains for insn luid 1 uid 17
;; reg 125 { d4(bb 3 insn 23) }
;; reg 144 { }
;; eq_note reg 125 { d4(bb 3 insn 23) }
(insn 17 15 18 3 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(expr_list:REG_EQUAL (mem:V2DF (plus:DI (reg:DI 125 [ ivtmp.14 ])
(symbol_ref:DI ("x") [flags 0x80] <var_decl 0x3fff88d40510 x>)) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])
(nil))))
;; UD chains for insn luid 2 uid 18
;; reg 131 { d5(bb 3 insn 15) }
;; reg 133 { d6(bb 3 insn 17) }
(insn 18 17 19 3 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
;; UD chains for insn luid 3 uid 19
;; reg 121 { d2(bb 3 insn 18) }
(insn 19 18 20 3 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
;; UD chains for insn luid 4 uid 20
;; reg 120 { d1(bb 3 insn 19) }
;; reg 122 { d3(bb 3 insn 22) }
(insn 20 19 21 3 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
;; UD chains for insn luid 5 uid 21
;; reg 121 { d2(bb 3 insn 18) }
(insn 21 20 22 3 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
;; UD chains for insn luid 6 uid 22
;; reg 119 { d0(bb 3 insn 20) }
;; reg 134 { d7(bb 3 insn 21) }
(insn 22 21 23 3 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
;; UD chains for insn luid 7 uid 23
;; reg 125 { d4(bb 3 insn 23) }
(insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
;; UD chains for insn luid 8 uid 25
;; reg 125 { d4(bb 3 insn 23) }
(insn 25 23 26 3 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
;; UD chains for insn luid 9 uid 26
;; reg 135 { d8(bb 3 insn 25) }
(jump_insn 26 25 67 3 (set (pc)
(if_then_else (ne (reg:CCUNS 135)
(const_int 0 [0]))
(label_ref:DI 67)
(pc))) 794 {*cbranch}
(expr_list:REG_DEAD (reg:CCUNS 135)
(int_list:REG_BR_PROB 1052266990 (nil)))
-> 67)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; live out 122 125
;; rd out (2) 122[3],125[4]
;; UD chains for artificial uses at bottom
;; reg 1 { }
;; reg 2 { }
;; reg 31 { }
;; reg 99 { }
;; reg 110 { }
;; bb 8 artificial_defs: { }
;; bb 8 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; lr def
;; live in 122 125
;; live gen
;; live kill
;; rd in (9) 119[0],120[1],121[2],122[3],125[4],131[5],133[6],134[7],135[8]
;; rd gen (0)
;; rd kill (0)
;; UD chains for artificial uses at top
(code_label 67 26 66 8 5 (nil) [1 uses])
(note 66 67 27 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; live out 122 125
;; rd out (2) 122[3],125[4]
;; UD chains for artificial uses at bottom
;; reg 1 { }
;; reg 2 { }
;; reg 31 { }
;; reg 99 { }
;; reg 110 { }
changing bb of uid 69
unscanned insn
Redirecting fallthru edge 3->4 to 9
Analyzing (reg:DI 125 [ ivtmp.14 ]) for bivness.
(reg:DI 125 [ ivtmp.14 ]) + (const_int 16 [0x10]) * iteration (in DI)
Analyzing def of (reg:DI 125 [ ivtmp.14 ]) in insn (insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
Analyzing operand (reg:DI 125 [ ivtmp.14 ]) of insn (insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
Analyzing (reg:DI 125 [ ivtmp.14 ]) for bivness.
already analysed.
Analyzing operand (const_int 16 [0x10]) of insn (insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
invariant (const_int 16 [0x10]) (in DI)
(reg:DI 125 [ ivtmp.14 ]) in insn (insn 23 22 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
is (plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10])) + (const_int 16 [0x10]) * iteration (in DI)
;; Condition at end of loop.
changing bb of uid 81
unscanned insn
changing bb of uid 71
unscanned insn
deferring rescan insn with uid = 71.
changing bb of uid 72
unscanned insn
deferring rescan insn with uid = 72.
changing bb of uid 73
unscanned insn
deferring rescan insn with uid = 73.
changing bb of uid 74
unscanned insn
deferring rescan insn with uid = 74.
changing bb of uid 75
unscanned insn
deferring rescan insn with uid = 75.
changing bb of uid 76
unscanned insn
deferring rescan insn with uid = 76.
changing bb of uid 77
unscanned insn
deferring rescan insn with uid = 77.
changing bb of uid 78
unscanned insn
deferring rescan insn with uid = 78.
changing bb of uid 79
unscanned insn
deferring rescan insn with uid = 79.
changing bb of uid 80
unscanned insn
deferring rescan insn with uid = 80.
changing bb of uid 83
unscanned insn
deferring rescan insn with uid = 80.
Edge 10->8 redirected to 11
Redirecting fallthru edge 11->3 to 10
Redirecting fallthru edge 8->3 to 10
Redirecting fallthru edge 11->10 to 3
Making edge 10->9 impossible by redistributing probability to other edges.
changing bb of uid 96
unscanned insn
changing bb of uid 86
unscanned insn
deferring rescan insn with uid = 86.
changing bb of uid 87
unscanned insn
deferring rescan insn with uid = 87.
changing bb of uid 88
unscanned insn
deferring rescan insn with uid = 88.
changing bb of uid 89
unscanned insn
deferring rescan insn with uid = 89.
changing bb of uid 90
unscanned insn
deferring rescan insn with uid = 90.
changing bb of uid 91
unscanned insn
deferring rescan insn with uid = 91.
changing bb of uid 92
unscanned insn
deferring rescan insn with uid = 92.
changing bb of uid 93
unscanned insn
deferring rescan insn with uid = 93.
changing bb of uid 94
unscanned insn
deferring rescan insn with uid = 94.
changing bb of uid 95
unscanned insn
deferring rescan insn with uid = 95.
changing bb of uid 98
unscanned insn
deferring rescan insn with uid = 95.
Edge 12->8 redirected to 13
Redirecting fallthru edge 11->3 to 12
Redirecting fallthru edge 13->10 to 3
Making edge 12->9 impossible by redistributing probability to other edges.
changing bb of uid 111
unscanned insn
changing bb of uid 101
unscanned insn
deferring rescan insn with uid = 101.
changing bb of uid 102
unscanned insn
deferring rescan insn with uid = 102.
changing bb of uid 103
unscanned insn
deferring rescan insn with uid = 103.
changing bb of uid 104
unscanned insn
deferring rescan insn with uid = 104.
changing bb of uid 105
unscanned insn
deferring rescan insn with uid = 105.
changing bb of uid 106
unscanned insn
deferring rescan insn with uid = 106.
changing bb of uid 107
unscanned insn
deferring rescan insn with uid = 107.
changing bb of uid 108
unscanned insn
deferring rescan insn with uid = 108.
changing bb of uid 109
unscanned insn
deferring rescan insn with uid = 109.
changing bb of uid 110
unscanned insn
deferring rescan insn with uid = 110.
changing bb of uid 113
unscanned insn
deferring rescan insn with uid = 110.
Edge 14->8 redirected to 15
Redirecting fallthru edge 13->3 to 14
Redirecting fallthru edge 15->10 to 3
Making edge 14->9 impossible by redistributing probability to other edges.
changing bb of uid 126
unscanned insn
changing bb of uid 116
unscanned insn
deferring rescan insn with uid = 116.
changing bb of uid 117
unscanned insn
deferring rescan insn with uid = 117.
changing bb of uid 118
unscanned insn
deferring rescan insn with uid = 118.
changing bb of uid 119
unscanned insn
deferring rescan insn with uid = 119.
changing bb of uid 120
unscanned insn
deferring rescan insn with uid = 120.
changing bb of uid 121
unscanned insn
deferring rescan insn with uid = 121.
changing bb of uid 122
unscanned insn
deferring rescan insn with uid = 122.
changing bb of uid 123
unscanned insn
deferring rescan insn with uid = 123.
changing bb of uid 124
unscanned insn
deferring rescan insn with uid = 124.
changing bb of uid 125
unscanned insn
deferring rescan insn with uid = 125.
changing bb of uid 128
unscanned insn
deferring rescan insn with uid = 125.
Edge 16->8 redirected to 17
Redirecting fallthru edge 15->3 to 16
Redirecting fallthru edge 17->10 to 3
Making edge 16->9 impossible by redistributing probability to other edges.
changing bb of uid 141
unscanned insn
changing bb of uid 131
unscanned insn
deferring rescan insn with uid = 131.
changing bb of uid 132
unscanned insn
deferring rescan insn with uid = 132.
changing bb of uid 133
unscanned insn
deferring rescan insn with uid = 133.
changing bb of uid 134
unscanned insn
deferring rescan insn with uid = 134.
changing bb of uid 135
unscanned insn
deferring rescan insn with uid = 135.
changing bb of uid 136
unscanned insn
deferring rescan insn with uid = 136.
changing bb of uid 137
unscanned insn
deferring rescan insn with uid = 137.
changing bb of uid 138
unscanned insn
deferring rescan insn with uid = 138.
changing bb of uid 139
unscanned insn
deferring rescan insn with uid = 139.
changing bb of uid 140
unscanned insn
deferring rescan insn with uid = 140.
changing bb of uid 143
unscanned insn
deferring rescan insn with uid = 140.
Edge 18->8 redirected to 19
Redirecting fallthru edge 17->3 to 18
Redirecting fallthru edge 19->10 to 3
Making edge 18->9 impossible by redistributing probability to other edges.
changing bb of uid 156
unscanned insn
changing bb of uid 146
unscanned insn
deferring rescan insn with uid = 146.
changing bb of uid 147
unscanned insn
deferring rescan insn with uid = 147.
changing bb of uid 148
unscanned insn
deferring rescan insn with uid = 148.
changing bb of uid 149
unscanned insn
deferring rescan insn with uid = 149.
changing bb of uid 150
unscanned insn
deferring rescan insn with uid = 150.
changing bb of uid 151
unscanned insn
deferring rescan insn with uid = 151.
changing bb of uid 152
unscanned insn
deferring rescan insn with uid = 152.
changing bb of uid 153
unscanned insn
deferring rescan insn with uid = 153.
changing bb of uid 154
unscanned insn
deferring rescan insn with uid = 154.
changing bb of uid 155
unscanned insn
deferring rescan insn with uid = 155.
changing bb of uid 158
unscanned insn
deferring rescan insn with uid = 155.
Edge 20->8 redirected to 21
Redirecting fallthru edge 19->3 to 20
Redirecting fallthru edge 21->10 to 3
Making edge 20->9 impossible by redistributing probability to other edges.
changing bb of uid 171
unscanned insn
changing bb of uid 161
unscanned insn
deferring rescan insn with uid = 161.
changing bb of uid 162
unscanned insn
deferring rescan insn with uid = 162.
changing bb of uid 163
unscanned insn
deferring rescan insn with uid = 163.
changing bb of uid 164
unscanned insn
deferring rescan insn with uid = 164.
changing bb of uid 165
unscanned insn
deferring rescan insn with uid = 165.
changing bb of uid 166
unscanned insn
deferring rescan insn with uid = 166.
changing bb of uid 167
unscanned insn
deferring rescan insn with uid = 167.
changing bb of uid 168
unscanned insn
deferring rescan insn with uid = 168.
changing bb of uid 169
unscanned insn
deferring rescan insn with uid = 169.
changing bb of uid 170
unscanned insn
deferring rescan insn with uid = 170.
changing bb of uid 173
unscanned insn
deferring rescan insn with uid = 170.
Edge 22->8 redirected to 23
Redirecting fallthru edge 21->3 to 22
Redirecting fallthru edge 23->10 to 3
Making edge 3->9 impossible by redistributing probability to other edges.
deferring rescan insn with uid = 78.
deferring rescan insn with uid = 93.
deferring rescan insn with uid = 108.
deferring rescan insn with uid = 123.
deferring rescan insn with uid = 138.
deferring rescan insn with uid = 153.
deferring rescan insn with uid = 168.
deferring rescan insn with uid = 175.
deferring rescan insn with uid = 23.
changing bb of uid 176
unscanned insn
Redirecting fallthru edge 10->9 to 24
Removing jump 80.
deferring deletion of insn with uid = 80.
deleting block 24
changing bb of uid 177
unscanned insn
Redirecting fallthru edge 12->9 to 25
Removing jump 95.
deferring deletion of insn with uid = 95.
deleting block 25
changing bb of uid 178
unscanned insn
Redirecting fallthru edge 14->9 to 26
Removing jump 110.
deferring deletion of insn with uid = 110.
deleting block 26
changing bb of uid 179
unscanned insn
Redirecting fallthru edge 16->9 to 27
Removing jump 125.
deferring deletion of insn with uid = 125.
deleting block 27
changing bb of uid 180
unscanned insn
Redirecting fallthru edge 18->9 to 28
Removing jump 140.
deferring deletion of insn with uid = 140.
deleting block 28
changing bb of uid 181
unscanned insn
Redirecting fallthru edge 20->9 to 29
Removing jump 155.
deferring deletion of insn with uid = 155.
deleting block 29
changing bb of uid 182
unscanned insn
Redirecting fallthru edge 3->9 to 30
Removing jump 26.
deferring deletion of insn with uid = 26.
deleting block 30
;; Unrolled loop 7 times, constant # of iterations 74 insns
fix_loop_structure: fixing up loops for function
starting the processing of deferred insns
rescanning insn with uid = 23.
rescanning insn with uid = 71.
rescanning insn with uid = 72.
rescanning insn with uid = 73.
rescanning insn with uid = 74.
rescanning insn with uid = 75.
rescanning insn with uid = 76.
rescanning insn with uid = 77.
rescanning insn with uid = 78.
rescanning insn with uid = 79.
rescanning insn with uid = 86.
rescanning insn with uid = 87.
rescanning insn with uid = 88.
rescanning insn with uid = 89.
rescanning insn with uid = 90.
rescanning insn with uid = 91.
rescanning insn with uid = 92.
rescanning insn with uid = 93.
rescanning insn with uid = 94.
rescanning insn with uid = 101.
rescanning insn with uid = 102.
rescanning insn with uid = 103.
rescanning insn with uid = 104.
rescanning insn with uid = 105.
rescanning insn with uid = 106.
rescanning insn with uid = 107.
rescanning insn with uid = 108.
rescanning insn with uid = 109.
rescanning insn with uid = 116.
rescanning insn with uid = 117.
rescanning insn with uid = 118.
rescanning insn with uid = 119.
rescanning insn with uid = 120.
rescanning insn with uid = 121.
rescanning insn with uid = 122.
rescanning insn with uid = 123.
rescanning insn with uid = 124.
rescanning insn with uid = 131.
rescanning insn with uid = 132.
rescanning insn with uid = 133.
rescanning insn with uid = 134.
rescanning insn with uid = 135.
rescanning insn with uid = 136.
rescanning insn with uid = 137.
rescanning insn with uid = 138.
rescanning insn with uid = 139.
rescanning insn with uid = 146.
rescanning insn with uid = 147.
rescanning insn with uid = 148.
rescanning insn with uid = 149.
rescanning insn with uid = 150.
rescanning insn with uid = 151.
rescanning insn with uid = 152.
rescanning insn with uid = 153.
rescanning insn with uid = 154.
rescanning insn with uid = 161.
rescanning insn with uid = 162.
rescanning insn with uid = 163.
rescanning insn with uid = 164.
rescanning insn with uid = 165.
rescanning insn with uid = 166.
rescanning insn with uid = 167.
rescanning insn with uid = 168.
rescanning insn with uid = 169.
rescanning insn with uid = 170.
rescanning insn with uid = 175.
ending the processing of deferred insns
main
Dataflow summary:
;; invalidated by call 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr]
;; hardware regs used 1 [1] 2 [2] 99 [ap] 109 [vscr] 110 [sfp]
;; regular block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; eh block artificial uses 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; entry block defs 1 [1] 2 [2] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 31 [31] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 96 [lr] 99 [ap] 109 [vscr] 110 [sfp]
;; exit block uses 1 [1] 2 [2] 3 [3] 31 [31] 108 [vrsave] 109 [vscr] 110 [sfp]
;; regs ever live 1 [1] 2 [2] 3 [3] 4 [4] 33 [1] 96 [lr] 109 [vscr]
;; ref usage r0={3d} r1={1d,26u} r2={1d,32u} r3={5d,2u} r4={5d,1u} r5={4d} r6={4d} r7={4d} r8={4d} r9={4d} r10={4d} r11={3d} r12={3d} r13={3d} r31={1d,23u} r32={3d} r33={5d,1u} r34={4d} r35={4d} r36={4d} r37={4d} r38={4d} r39={4d} r40={4d} r41={4d} r42={4d} r43={4d} r44={4d} r45={4d} r64={3d} r65={3d} r66={4d} r67={4d} r68={4d} r69={4d} r70={4d} r71={4d} r72={4d} r73={4d} r74={4d} r75={4d} r76={4d} r77={4d} r78={3d} r79={3d} r80={3d} r81={3d} r82={3d} r83={3d} r96={4d} r97={3d} r98={3d} r99={1d,22u} r100={3d} r101={3d} r105={3d} r106={3d} r107={3d} r108={1u} r109={4d,4u} r110={1d,23u} r119={8d,8u} r120={8d,8u} r121={8d,16u} r122={9d,9u} r125={9d,25u} r126={2d,2u} r131={8d,8u} r133={8d,8u} r134={8d,8u} r135={8d,1u} r136={1d,1u} r137={1d,1u} r138={1d,1u} r140={1d,1u} r141={1d,1u} r142={1d,1u} r144={1d,8u} r145={1d,8u} r146={1d,1u} r147={1d,8u}
;; total ref usage 553{294d,259u,0e} in 97{94 regular + 3 call} insns.
;; basic block 2, loop depth 0, count 108459 (estimated locally), maybe hot
;; prev block 0, next block 3, flags: (REACHABLE, RTL, MODIFIED)
;; pred: ENTRY [always] count:108459 (estimated locally) (FALLTHRU)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(1){ }u1(2){ }u2(31){ }u3(99){ }u4(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; lr def 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] 126 144 145 146
;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; live gen 109 [vscr] 126 144 145 146
;; live kill 96 [lr]
(note 8 0 4 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 4 8 10 2 NOTE_INSN_FUNCTION_BEG)
(call_insn 10 4 7 2 (parallel [
(call (mem:SI (symbol_ref:DI ("first_dummy") [flags 0x41] <function_decl 0x3fff863be000 first_dummy>) [0 first_dummy S4 A8])
(const_int 64 [0x40]))
(clobber (reg:DI 96 lr))
]) "p9-dform-0.c":26:3 704 {*call_nonlocal_aixdi}
(expr_list:REG_CALL_DECL (symbol_ref:DI ("first_dummy") [flags 0x41] <function_decl 0x3fff863be000 first_dummy>)
(nil))
(expr_list (use (reg:DI 2 2))
(nil)))
(insn 7 10 63 2 (set (reg:DI 126 [ ivtmp_28 ])
(const_int 128 [0x80])) "p9-dform-0.c":26:3 609 {*movdi_internal64}
(nil))
(insn 63 7 64 2 (set (reg/f:DI 145)
(mem/u/c:DI (unspec:DI [
(symbol_ref/u:DI ("*.LC0") [flags 0x2])
(reg:DI 2 2)
] UNSPEC_TOCREL) [4 S8 A8])) 609 {*movdi_internal64}
(expr_list:REG_EQUAL (symbol_ref:DI ("y") [flags 0x80] <var_decl 0x3fff88d405a0 y>)
(nil)))
(insn 64 63 6 2 (set (reg/f:DI 144)
(mem/u/c:DI (unspec:DI [
(symbol_ref/u:DI ("*.LC1") [flags 0x2])
(reg:DI 2 2)
] UNSPEC_TOCREL) [4 S8 A8])) 609 {*movdi_internal64}
(expr_list:REG_EQUAL (symbol_ref:DI ("x") [flags 0x80] <var_decl 0x3fff88d40510 x>)
(nil)))
(insn 6 64 24 2 (set (reg:DF 146 [ sacc ])
(const_double:DF 0.0 [0x0.0p+0])) "p9-dform-0.c":29:10 512 {*movdf_hardfloat64}
(nil))
;; succ: 5 [always] count:108459 (estimated locally) (FALLTHRU)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp] 126 144 145
;; live out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145
;; basic block 3, loop depth 2, count 67108863 (estimated locally), maybe hot
;; Invalid sum of incoming counts 76504103 (estimated locally), should be 67108863 (estimated locally)
;; prev block 2, next block 9, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 5 [always] count:10737418 (estimated locally) (FALLTHRU)
;; 23 [always] count:65766685 (estimated locally) (FALLTHRU)
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u8(1){ }u9(2){ }u10(31){ }u11(99){ }u12(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 122 125 144 145
;; lr def 119 120 121 122 125 131 133 134 135
;; live in 122 125
;; live gen 119 120 121 122 125 131 133 134 135
;; live kill
(code_label 24 6 13 3 3 (nil) [0 uses])
(note 13 24 15 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 15 13 17 3 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(nil)))
(insn 17 15 18 3 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(nil)))
(insn 18 17 19 3 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
(insn 19 18 20 3 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
(insn 20 19 21 3 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
(insn 21 20 22 3 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
(insn 22 21 175 3 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
(insn 175 22 23 3 (set (reg:DI 147)
(plus:DI (reg:DI 125 [ ivtmp.14 ])
(const_int 16 [0x10]))) -1
(nil))
(insn 23 175 25 3 (set (reg:DI 125 [ ivtmp.14 ])
(reg:DI 147)) 609 {*movdi_internal64}
(nil))
(insn 25 23 69 3 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
;; succ: 8 [always] count:67108863 (estimated locally) (FALLTHRU)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; live out 122 125
;; basic block 9, loop depth 1, count 10737420 (estimated locally), maybe hot
;; Invalid sum of incoming counts 1342177 (estimated locally), should be 10737420 (estimated locally)
;; prev block 3, next block 8, flags: (NEW, RTL, MODIFIED)
;; pred: 22 [2.0% (adjusted)] count:1342177 (estimated locally) (FALLTHRU,LOOP_EXIT)
;; bb 9 artificial_defs: { }
;; bb 9 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in
;; lr use
;; lr def
;; live in
;; live gen
;; live kill
(note 69 25 67 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
;; succ: 4 [always] count:10737420 (estimated locally) (FALLTHRU)
;; lr out
;; live out
;; basic block 8, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 9, next block 4, flags: (NEW, REACHABLE, RTL, MODIFIED)
;; pred: 3 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 8 artificial_defs: { }
;; bb 8 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; lr def
;; live in 122 125
;; live gen
;; live kill
(code_label 67 69 66 8 5 (nil) [0 uses])
(note 66 67 27 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
;; succ: 10 [always] count:67108863 (estimated locally) (FALLTHRU)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 144 145
;; live out 122 125
;; basic block 4, loop depth 1, count 10737418 (estimated locally), maybe hot
;; prev block 8, next block 7, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 9 [always] count:10737420 (estimated locally) (FALLTHRU)
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u30(1){ }u31(2){ }u32(31){ }u33(99){ }u34(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 126 144 145 146
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 126
;; lr def 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] 126 136 137
;; live in 109 [vscr] 122 126
;; live gen 4 [4] 33 [1] 109 [vscr] 126 136 137
;; live kill 96 [lr]
(note 27 66 28 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 28 27 29 4 (set (reg:DI 4 4)
(const_int 512 [0x200])) "p9-dform-0.c":33:5 609 {*movdi_internal64}
(nil))
(insn 29 28 30 4 (set (reg:DF 33 1)
(reg/v:DF 122 [ sacc ])) "p9-dform-0.c":33:5 512 {*movdf_hardfloat64}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(nil)))
(call_insn 30 29 31 4 (parallel [
(call (mem:SI (symbol_ref:DI ("dummy") [flags 0x41] <function_decl 0x3fff863be100 dummy>) [0 dummy S4 A8])
(const_int 0 [0]))
(clobber (reg:DI 96 lr))
]) "p9-dform-0.c":33:5 704 {*call_nonlocal_aixdi}
(expr_list:REG_DEAD (reg:DF 33 1)
(expr_list:REG_DEAD (reg:DI 4 4)
(expr_list:REG_CALL_DECL (symbol_ref:DI ("dummy") [flags 0x41] <function_decl 0x3fff863be100 dummy>)
(nil))))
(expr_list (use (reg:DI 2 2))
(expr_list:DF (use (reg:DF 33 1))
(expr_list:SI (use (reg:DI 4 4))
(nil)))))
(insn 31 30 32 4 (set (reg:SI 136)
(plus:SI (subreg/s/v:SI (reg:DI 126 [ ivtmp_28 ]) 0)
(const_int -1 [0xffffffffffffffff]))) "p9-dform-0.c":27:3 68 {*addsi3}
(expr_list:REG_DEAD (reg:DI 126 [ ivtmp_28 ])
(nil)))
(insn 32 31 33 4 (set (reg:DI 126 [ ivtmp_28 ])
(zero_extend:DI (reg:SI 136))) "p9-dform-0.c":27:3 19 {zero_extendsidi2}
(expr_list:REG_DEAD (reg:SI 136)
(nil)))
(insn 33 32 34 4 (set (reg:CC 137)
(compare:CC (reg:DI 126 [ ivtmp_28 ])
(const_int 0 [0]))) "p9-dform-0.c":27:3 730 {*cmpdi_signed}
(nil))
(jump_insn 34 33 65 4 (set (pc)
(if_then_else (eq (reg:CC 137)
(const_int 0 [0]))
(label_ref 39)
(pc))) "p9-dform-0.c":27:3 794 {*cbranch}
(expr_list:REG_DEAD (reg:CC 137)
(int_list:REG_BR_PROB 10845908 (nil)))
-> 39)
;; succ: 7 [99.0% (guessed)] count:10628959 (estimated locally) (FALLTHRU,DFS_BACK)
;; 6 [1.0% (guessed)] count:108459 (estimated locally) (LOOP_EXIT)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145 146
;; live out 109 [vscr] 126
;; basic block 7, loop depth 1, count 10628959 (estimated locally), maybe hot
;; prev block 4, next block 5, flags: (NEW, REACHABLE, RTL, MODIFIED)
;; pred: 4 [99.0% (guessed)] count:10628959 (estimated locally) (FALLTHRU,DFS_BACK)
;; bb 7 artificial_defs: { }
;; bb 7 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145 146
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp]
;; lr def
;; live in 109 [vscr] 126
;; live gen
;; live kill
(note 65 34 35 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
;; succ: 5 [always] count:10628959 (estimated locally) (FALLTHRU)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145 146
;; live out 109 [vscr] 126
;; basic block 5, loop depth 1, count 10737418 (estimated locally), maybe hot
;; prev block 7, next block 6, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 2 [always] count:108459 (estimated locally) (FALLTHRU)
;; 7 [always] count:10628959 (estimated locally) (FALLTHRU)
;; bb 5 artificial_defs: { }
;; bb 5 artificial_uses: { u45(1){ }u46(2){ }u47(31){ }u48(99){ }u49(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 126 144 145 146
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 110 [sfp] 146
;; lr def 122 125
;; live in 109 [vscr] 126
;; live gen 122 125
;; live kill
(code_label 35 65 36 5 2 (nil) [0 uses])
(note 36 35 5 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(insn 5 36 68 5 (set (reg:DI 125 [ ivtmp.14 ])
(const_int 0 [0])) "p9-dform-0.c":23:36 609 {*movdi_internal64}
(nil))
(insn 68 5 39 5 (set (reg/v:DF 122 [ sacc ])
(reg:DF 146 [ sacc ])) "p9-dform-0.c":29:10 512 {*movdf_hardfloat64}
(expr_list:REG_DEAD (reg:DF 146 [ sacc ])
(nil)))
;; succ: 3 [always] count:10737418 (estimated locally) (FALLTHRU)
;; lr out 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp] 122 125 126 144 145 146
;; live out 109 [vscr] 122 125 126
;; basic block 6, loop depth 0, count 108459 (estimated locally), maybe hot
;; prev block 5, next block 10, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 4 [1.0% (guessed)] count:108459 (estimated locally) (LOOP_EXIT)
;; bb 6 artificial_defs: { }
;; bb 6 artificial_uses: { u50(1){ }u51(2){ }u52(31){ }u53(99){ }u54(110){ }}
;; lr in 1 [1] 2 [2] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; lr use 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; lr def 0 [0] 3 [3] 4 [4] 5 [5] 6 [6] 7 [7] 8 [8] 9 [9] 10 [10] 11 [11] 12 [12] 13 [13] 32 [0] 33 [1] 34 [2] 35 [3] 36 [4] 37 [5] 38 [6] 39 [7] 40 [8] 41 [9] 42 [10] 43 [11] 44 [12] 45 [13] 64 [0] 65 [1] 66 [2] 67 [3] 68 [4] 69 [5] 70 [6] 71 [7] 72 [8] 73 [9] 74 [10] 75 [11] 76 [12] 77 [13] 78 [14] 79 [15] 80 [16] 81 [17] 82 [18] 83 [19] 96 [lr] 97 [ctr] 98 [ca] 100 [0] 101 [1] 105 [5] 106 [6] 107 [7] 109 [vscr] 138 140 141 142
;; live in 1 [1] 2 [2] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; live gen 3 [3] 109 [vscr] 138 140 141 142
;; live kill 96 [lr]
(code_label 39 68 40 6 4 (nil) [1 uses])
(note 40 39 41 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
;; get address of opt_value
(insn 41 40 43 6 (set (reg/f:DI 138)
(mem/u/c:DI (unspec:DI [
(symbol_ref/u:DI ("*.LC2") [flags 0x2])
(reg:DI 2 2)
] UNSPEC_TOCREL) [4 S8 A8])) "p9-dform-0.c":35:13 609 {*movdi_internal64}
(expr_list:REG_EQUAL (symbol_ref:DI ("opt_value") [flags 0xc0] <var_decl 0x3fff88d403f0 opt_value>)
(nil)))
;; must be folded constant expression as a float
(insn 43 41 44 6 (set (reg:SF 140)
(mem/u/c:SF (unspec:DI [
(symbol_ref/u:DI ("*.LC3") [flags 0x82])
(reg:DI 2 2)
] UNSPEC_TOCREL) [0 S4 A32])) "p9-dform-0.c":35:13 503 {movsf_hardfloat}
(expr_list:REG_EQUAL (const_double:SF 1.31072e+5 [0x0.8p+18])
(nil)))
;; overwrite opt_value
(insn 44 43 45 6 (set (mem/c:SF (reg/f:DI 138) [2 opt_value+0 S4 A32])
(reg:SF 140)) "p9-dform-0.c":35:13 503 {movsf_hardfloat}
(expr_list:REG_DEAD (reg:SF 140)
(expr_list:REG_DEAD (reg/f:DI 138)
(nil))))
;; get address of opt_desc
(insn 45 44 46 6 (set (reg/f:DI 141)
(mem/u/c:DI (unspec:DI [
(symbol_ref/u:DI ("*.LC4") [flags 0x2])
(reg:DI 2 2)
] UNSPEC_TOCREL) [4 S8 A8])) "p9-dform-0.c":36:12 609 {*movdi_internal64}
(expr_list:REG_EQUAL (symbol_ref:DI ("opt_desc") [flags 0xc0] <var_decl 0x3fff88d40480 opt_desc>)
(nil)))
;; overwrite opt_desc
(insn 46 45 47 6 (set (reg/f:DI 142)
(unspec:DI [
(symbol_ref/f:DI ("*.LC5") [flags 0x82] <var_decl 0x3fff88d41b00 *.LC5>)
(reg:DI 2 2)
] UNSPEC_TOCREL)) "p9-dform-0.c":36:12 685 {*tocrefdi}
(expr_list:REG_EQUAL (symbol_ref/f:DI ("*.LC5") [flags 0x82] <var_decl 0x3fff88d41b00 *.LC5>)
(nil)))
(insn 47 46 48 6 (set (mem/f/c:DI (reg/f:DI 141) [3 opt_desc+0 S8 A64])
(reg/f:DI 142)) "p9-dform-0.c":36:12 609 {*movdi_internal64}
(expr_list:REG_DEAD (reg/f:DI 142)
(expr_list:REG_DEAD (reg/f:DI 141)
(nil))))
;; call other_dummy
(call_insn 48 47 53 6 (parallel [
(call (mem:SI (symbol_ref:DI ("other_dummy") [flags 0x41] <function_decl 0x3fff863be200 other_dummy>) [0 other_dummy S4 A8])
(const_int 64 [0x40]))
(clobber (reg:DI 96 lr))
]) "p9-dform-0.c":37:3 704 {*call_nonlocal_aixdi}
(expr_list:REG_CALL_DECL (symbol_ref:DI ("other_dummy") [flags 0x41] <function_decl 0x3fff863be200 other_dummy>)
(nil))
(expr_list (use (reg:DI 2 2))
(nil)))
(insn 53 48 54 6 (set (reg/i:DI 3 3)
(const_int 0 [0])) "p9-dform-0.c":38:1 609 {*movdi_internal64}
(nil))
(insn 54 53 81 6 (use (reg/i:DI 3 3)) "p9-dform-0.c":38:1 -1
(nil))
;; succ: EXIT [always] count:108459 (estimated locally) (FALLTHRU)
;; lr out 1 [1] 2 [2] 3 [3] 31 [31] 99 [ap] 108 [vrsave] 109 [vscr] 110 [sfp]
;; live out 1 [1] 2 [2] 3 [3] 31 [31] 99 [ap] 109 [vscr] 110 [sfp]
;; basic block 10, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 6, next block 11, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 8 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 10 artificial_defs: { }
;; bb 10 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(note 81 54 71 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(insn 71 81 72 10 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(nil)))
(insn 72 71 73 10 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(nil)))
(insn 73 72 74 10 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
(insn 74 73 75 10 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
(insn 75 74 76 10 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
(insn 76 75 77 10 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
(insn 77 76 78 10 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
(insn 78 77 79 10 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 147)
(const_int 16 [0x10]))) 69 {*adddi3}
(nil))
(insn 79 78 84 10 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
;; succ: 11 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 11, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 10, next block 12, flags: (NEW, REACHABLE, RTL, MODIFIED)
;; pred: 10 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 11 artificial_defs: { }
;; bb 11 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(code_label 84 79 83 11 6 (nil) [0 uses])
(note 83 84 96 11 [bb 11] NOTE_INSN_BASIC_BLOCK)
;; succ: 12 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 12, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 11, next block 13, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 11 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 12 artificial_defs: { }
;; bb 12 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(note 96 83 86 12 [bb 12] NOTE_INSN_BASIC_BLOCK)
(insn 86 96 87 12 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(nil)))
(insn 87 86 88 12 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(nil)))
(insn 88 87 89 12 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
(insn 89 88 90 12 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
(insn 90 89 91 12 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
(insn 91 90 92 12 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
(insn 92 91 93 12 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
(insn 93 92 94 12 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 147)
(const_int 32 [0x20]))) 69 {*adddi3}
(nil))
(insn 94 93 99 12 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
;; succ: 13 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 13, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 12, next block 14, flags: (NEW, REACHABLE, RTL, MODIFIED)
;; pred: 12 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 13 artificial_defs: { }
;; bb 13 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(code_label 99 94 98 13 7 (nil) [0 uses])
(note 98 99 111 13 [bb 13] NOTE_INSN_BASIC_BLOCK)
;; succ: 14 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 14, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 13, next block 15, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 13 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 14 artificial_defs: { }
;; bb 14 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(note 111 98 101 14 [bb 14] NOTE_INSN_BASIC_BLOCK)
(insn 101 111 102 14 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(nil)))
(insn 102 101 103 14 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(nil)))
(insn 103 102 104 14 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
(insn 104 103 105 14 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
(insn 105 104 106 14 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
(insn 106 105 107 14 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
(insn 107 106 108 14 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
(insn 108 107 109 14 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 147)
(const_int 48 [0x30]))) 69 {*adddi3}
(nil))
(insn 109 108 114 14 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
;; succ: 15 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 15, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 14, next block 16, flags: (NEW, REACHABLE, RTL, MODIFIED)
;; pred: 14 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 15 artificial_defs: { }
;; bb 15 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(code_label 114 109 113 15 8 (nil) [0 uses])
(note 113 114 126 15 [bb 15] NOTE_INSN_BASIC_BLOCK)
;; succ: 16 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 16, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 15, next block 17, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 15 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 16 artificial_defs: { }
;; bb 16 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(note 126 113 116 16 [bb 16] NOTE_INSN_BASIC_BLOCK)
(insn 116 126 117 16 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(nil)))
(insn 117 116 118 16 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(nil)))
(insn 118 117 119 16 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
(insn 119 118 120 16 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
(insn 120 119 121 16 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
(insn 121 120 122 16 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
(insn 122 121 123 16 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
(insn 123 122 124 16 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 147)
(const_int 64 [0x40]))) 69 {*adddi3}
(nil))
(insn 124 123 129 16 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
;; succ: 17 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 17, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 16, next block 18, flags: (NEW, REACHABLE, RTL, MODIFIED)
;; pred: 16 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 17 artificial_defs: { }
;; bb 17 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(code_label 129 124 128 17 9 (nil) [0 uses])
(note 128 129 141 17 [bb 17] NOTE_INSN_BASIC_BLOCK)
;; succ: 18 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 18, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 17, next block 19, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 17 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 18 artificial_defs: { }
;; bb 18 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(note 141 128 131 18 [bb 18] NOTE_INSN_BASIC_BLOCK)
(insn 131 141 132 18 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(nil)))
(insn 132 131 133 18 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(nil)))
(insn 133 132 134 18 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
(insn 134 133 135 18 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
(insn 135 134 136 18 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
(insn 136 135 137 18 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
(insn 137 136 138 18 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
(insn 138 137 139 18 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 147)
(const_int 80 [0x50]))) 69 {*adddi3}
(nil))
(insn 139 138 144 18 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
;; succ: 19 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 19, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 18, next block 20, flags: (NEW, REACHABLE, RTL, MODIFIED)
;; pred: 18 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 19 artificial_defs: { }
;; bb 19 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(code_label 144 139 143 19 10 (nil) [0 uses])
(note 143 144 156 19 [bb 19] NOTE_INSN_BASIC_BLOCK)
;; succ: 20 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 20, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 19, next block 21, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 19 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 20 artificial_defs: { }
;; bb 20 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(note 156 143 146 20 [bb 20] NOTE_INSN_BASIC_BLOCK)
(insn 146 156 147 20 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(nil)))
(insn 147 146 148 20 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(nil)))
(insn 148 147 149 20 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
(insn 149 148 150 20 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
(insn 150 149 151 20 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
(insn 151 150 152 20 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
(insn 152 151 153 20 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
(insn 153 152 154 20 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 147)
(const_int 96 [0x60]))) 69 {*adddi3}
(nil))
(insn 154 153 159 20 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
;; succ: 21 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 21, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 20, next block 22, flags: (NEW, REACHABLE, RTL, MODIFIED)
;; pred: 20 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 21 artificial_defs: { }
;; bb 21 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(code_label 159 154 158 21 11 (nil) [0 uses])
(note 158 159 171 21 [bb 21] NOTE_INSN_BASIC_BLOCK)
;; succ: 22 [always] count:67108863 (estimated locally) (FALLTHRU)
;; basic block 22, loop depth 2, count 67108863 (estimated locally), maybe hot
;; prev block 21, next block 23, flags: (REACHABLE, RTL, MODIFIED)
;; pred: 21 [always] count:67108863 (estimated locally) (FALLTHRU)
;; bb 22 artificial_defs: { }
;; bb 22 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(note 171 158 161 22 [bb 22] NOTE_INSN_BASIC_BLOCK)
(insn 161 171 162 22 (set (reg:V2DF 131 [ vect__2.8 ])
(mem:V2DF (plus:DI (reg/f:DI 145)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: y, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:23 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 145)
(nil)))
(insn 162 161 163 22 (set (reg:V2DF 133 [ vect__1.5 ])
(mem:V2DF (plus:DI (reg/f:DI 144)
(reg:DI 125 [ ivtmp.14 ])) [1 MEM[symbol: x, index: ivtmp.14_25, offset: 0B]+0 S16 A64])) "p9-dform-0.c":31:16 1073 {vsx_movv2df_64bit}
(expr_list:REG_DEAD (reg/f:DI 144)
(nil)))
(insn 163 162 164 22 (set (reg:V2DF 121 [ vect__3.9 ])
(mult:V2DF (reg:V2DF 131 [ vect__2.8 ])
(reg:V2DF 133 [ vect__1.5 ]))) "p9-dform-0.c":31:20 1108 {*vsx_mulv2df3}
(expr_list:REG_DEAD (reg:V2DF 133 [ vect__1.5 ])
(expr_list:REG_DEAD (reg:V2DF 131 [ vect__2.8 ])
(nil))))
(insn 164 163 165 22 (set (reg:DF 120 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 0 [0])
]))) 1259 {vsx_extract_v2df}
(nil))
(insn 165 164 166 22 (set (reg:DF 119 [ stmp_sacc_16.10 ])
(plus:DF (reg:DF 120 [ stmp_sacc_16.10 ])
(reg/v:DF 122 [ sacc ]))) 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg/v:DF 122 [ sacc ])
(expr_list:REG_DEAD (reg:DF 120 [ stmp_sacc_16.10 ])
(nil))))
(insn 166 165 167 22 (set (reg:DF 134 [ stmp_sacc_16.10 ])
(vec_select:DF (reg:V2DF 121 [ vect__3.9 ])
(parallel [
(const_int 1 [0x1])
]))) "p9-dform-0.c":31:12 1259 {vsx_extract_v2df}
(expr_list:REG_DEAD (reg:V2DF 121 [ vect__3.9 ])
(nil)))
(insn 167 166 168 22 (set (reg/v:DF 122 [ sacc ])
(plus:DF (reg:DF 134 [ stmp_sacc_16.10 ])
(reg:DF 119 [ stmp_sacc_16.10 ]))) "p9-dform-0.c":31:12 289 {*adddf3_fpr}
(expr_list:REG_DEAD (reg:DF 134 [ stmp_sacc_16.10 ])
(expr_list:REG_DEAD (reg:DF 119 [ stmp_sacc_16.10 ])
(nil))))
(insn 168 167 169 22 (set (reg:DI 125 [ ivtmp.14 ])
(plus:DI (reg:DI 147)
(const_int 112 [0x70]))) 69 {*adddi3}
(nil))
(insn 169 168 170 22 (set (reg:CCUNS 135)
(compare:CCUNS (reg:DI 125 [ ivtmp.14 ])
(const_int 4096 [0x1000]))) 732 {*cmpdi_unsigned}
(nil))
(jump_insn 170 169 174 22 (set (pc)
(if_then_else (ne (reg:CCUNS 135)
(const_int 0 [0]))
(label_ref:DI 174)
(pc))) 794 {*cbranch}
(expr_list:REG_DEAD (reg:CCUNS 135)
(int_list:REG_BR_PROB 1052266990 (nil)))
-> 174)
;; succ: 23 [98.0% (adjusted)] count:65766686 (estimated locally) (DFS_BACK)
;; 9 [2.0% (adjusted)] count:1342177 (estimated locally) (FALLTHRU,LOOP_EXIT)
;; basic block 23, loop depth 2, count 65766685 (estimated locally), maybe hot
;; prev block 22, next block 1, flags: (NEW, REACHABLE, RTL, MODIFIED)
;; pred: 22 [98.0% (adjusted)] count:65766686 (estimated locally) (DFS_BACK)
;; bb 23 artificial_defs: { }
;; bb 23 artificial_uses: { u-1(1){ }u-1(2){ }u-1(31){ }u-1(99){ }u-1(110){ }}
(code_label 174 170 173 23 12 (nil) [1 uses])
(note 173 174 0 23 [bb 23] NOTE_INSN_BASIC_BLOCK)
;; succ: 3 [always] count:65766685 (estimated locally) (FALLTHRU)