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[PATCH] [AArch64, Falkor] Adjust Falkor's sign extend reg+reg address cost
- From: Luis Machado <luis dot machado at linaro dot org>
- To: gcc-patches at gcc dot gnu dot org
- Cc: james dot greenhalgh at arm dot com, Richard dot Earnshaw at arm dot com
- Date: Wed, 25 Jul 2018 15:35:23 -0300
- Subject: [PATCH] [AArch64, Falkor] Adjust Falkor's sign extend reg+reg address cost
Adjust Falkor's register_sextend cost from 4 to 3. This fixes a testsuite
failure in gcc.target/aarch64/extend.c:ldr_sxtw where GCC was generating
a sbfiz instruction rather than a load with sign extension.
No performance changes.
gcc/ChangeLog:
2018-07-25 Luis Machado <luis.machado@linaro.org>
* config/aarch64/aarch64.c (qdf24xx_addrcost_table)
<register_sextend>: Set to 3.
---
gcc/config/aarch64/aarch64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index fa01475..ea39272 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -329,7 +329,7 @@ static const struct cpu_addrcost_table qdf24xx_addrcost_table =
1, /* pre_modify */
1, /* post_modify */
3, /* register_offset */
- 4, /* register_sextend */
+ 3, /* register_sextend */
3, /* register_zextend */
2, /* imm_offset */
};
--
2.7.4