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[PATCH, ARM, doc] add missing -mtune options
- From: Jim Wilson <jim dot wilson at linaro dot org>
- To: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Thu, 7 May 2015 15:12:18 -0700
- Subject: [PATCH, ARM, doc] add missing -mtune options
- Authentication-results: sourceware.org; auth=none
I noticed that the list of -mtune options in the arm-cores.def file
didn't match the list in the doc/invoke.texi file. There are 3 cores
missing: generic-armv7-a, cortex-a17, and cortex-a17.cortex-a7. This
patch adds the missing cores to the docs.
Jim
2015-05-07 Jim Wilson <jim.wilson@linaro.org>
* doc/invoke.texi (ARM Options, mtune): Add generic-armv7-a,
cortex-a17, and cortex-a17.cortex-a7.
Index: doc/invoke.texi
===================================================================
--- doc/invoke.texi (revision 222861)
+++ doc/invoke.texi (working copy)
@@ -13245,9 +13245,9 @@
@samp{arm10e}, @samp{arm1020e}, @samp{arm1022e},
@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
-@samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9},
-@samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53},
-@samp{cortex-a57}, @samp{cortex-a72},
+@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
+@samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
+@samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
@samp{cortex-r4},
@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m7},
@samp{cortex-m4},
@@ -13267,8 +13267,8 @@
Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible names are:
-@samp{cortex-a15.cortex-a7}, @samp{cortex-a57.cortex-a53},
-@samp{cortex-a72.cortex-a53}.
+@samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7},
+@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}.
@option{-mtune=generic-@var{arch}} specifies that GCC should tune the
performance for a blend of processors within architecture @var{arch}.