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Re: [PATCH, i386, MPX 1/X] Support of Intel MPX ISA. 2/2 New registers and instructions

From: Ilya Enkovich <enkovich dot gnu at gmail dot com>
To: Uros Bizjak <ubizjak at gmail dot com>
Cc: gcc-patches at gcc dot gnu dot org, joseph at codesourcery dot com, jakub at redhat dot com, areg dot melikadamyan at gmail dot com
Date: Tue, 17 Sep 2013 12:41:03 +0400
Subject: Re: [PATCH, i386, MPX 1/X] Support of Intel MPX ISA. 2/2 New registers and instructions
Authentication-results: sourceware.org; auth=none
References: <CAMbmDYamg+jwEY6FiZ_+_DT8nqug58Gi5Nf2PSDZ26Bi17K5=A at mail dot gmail dot com> <Pine dot LNX dot 4 dot 64 dot 1308092323090 dot 30018 at digraph dot polyomino dot org dot uk> <CAMbmDYbzeg05JsEv2hWQwQHoDZLzfeWC9spz-XH_a0ZERcYBEw at mail dot gmail dot com> <CAMbmDYa6Vc9_c84ZMRzE3sUMH7B0=VtaumSXzWE6yDVZjsEhdA at mail dot gmail dot com> <CAMbmDYb2K+bm0n7N8xnuGDOVezBMVqD3NuAOu0Qyg0UwpQ+tWA at mail dot gmail dot com> <CAMbmDYa+PMNQJCvhPDsPb-o5iaxcJmCJE2JFyaqJYS+-HM56Vw at mail dot gmail dot com> <CAMbmDYb9eS4K4gwpA04vEoDWJ50HwwgP76FE5b1vn=SqNgdTnQ at mail dot gmail dot com> <CAFULd4Z1Fzur6oSMwXpJKoAtv1BGUX8LFPNjzFMM2Mi1sZUpPQ at mail dot gmail dot com> <CAMbmDYYn+B7PVA+bmvuqmAxF9ApR6kSxe84t0zTmW+55xHbsUw at mail dot gmail dot com> <CAFULd4ZHbzk6U3jdmH-SHT0vyu-DZZa82mCKTk2BdvhSo2VLCQ at mail dot gmail dot com>

On 16 Sep 11:24, Uros Bizjak wrote:
> On Fri, Sep 13, 2013 at 12:18 PM, Ilya Enkovich <enkovich.gnu@gmail.com> wrote:
> > 2013/9/11 Uros Bizjak <ubizjak@gmail.com>:
> >>
> >
> > Hi Uros,
> >
> > Thanks a lot for the review!
> >
> >> The x86 part looks mostly OK (I have a couple of comments bellow), but
> >> please first get target-independent changes reviewed and committed.
> >
> > Do you mean I should move bound type and mode declaration into a separate patch?
> 
> Yes, target-independent part (middle end) has to go through the
> separate review to check if this part is OK. The target-dependent part
> uses the infrastructure from the middle end, so it can go into the
> code base only after target-independent parts are committed.

I sent a separate patch for bound type and mode class (http://gcc.gnu.org/ml/gcc-patches/2013-09/msg01268.html). Here is target part of the patch with fixes you mentioned. Does it look OK?

Bootstrapped and checked on linux-x86_64. Still shows incorrect length attribute computation (described here http://gcc.gnu.org/ml/gcc/2013-07/msg00311.html).

Thanks,
Ilya
--

2013-09-16  Ilya Enkovich  <ilya.enkovich@intel.com>

	* config/i386/constraints.md (B): New.
	(Ti): New.
	(Tb): New.
	* config/i386/i386-c.c (ix86_target_macros_internal): Add __MPX__.
	* config/i386/i386-modes.def (BND32): New.
	(BND64): New.
	* config/i386/i386-protos.h (ix86_bnd_prefixed_insn_p): New.
	* config/i386/i386.c (isa_opts): Add mmpx.
	(regclass_map): Add bound registers.
	(dbx_register_map): Likewise.
	(dbx64_register_map): Likewise.
	(svr4_dbx_register_map): Likewise.
	(PTA_MPX): New.
	(ix86_option_override_internal): Support MPX ISA.
	(ix86_conditional_register_usage): Support bound registers.
	(print_reg): Likewise.
	(ix86_code_end): Add MPX bnd prefix.
	(output_set_got): Likewise.
	(ix86_output_call_insn): Likewise.
	(ix86_print_operand): Add '!' (MPX bnd) print prefix support.
	(ix86_print_operand_punct_valid_p): Likewise.
	(ix86_print_operand_address): Support UNSPEC_BNDMK_ADDR and
	UNSPEC_BNDMK_ADDR.
	(ix86_class_likely_spilled_p): Add bound regs support.
	(ix86_hard_regno_mode_ok): Likewise.
	(x86_order_regs_for_local_alloc): Likewise.
	(ix86_bnd_prefixed_insn_p): New.
	* config/i386/i386.h (FIRST_PSEUDO_REGISTER): Fix to new value.
	(FIXED_REGISTERS): Add bound registers.
	(CALL_USED_REGISTERS): Likewise.
	(REG_ALLOC_ORDER): Likewise.
	(HARD_REGNO_NREGS): Likewise.
	(TARGET_MPX): New.
	(VALID_BND_REG_MODE): New.
	(FIRST_BND_REG): New.
	(LAST_BND_REG): New.
	(reg_class): Add BND_REGS.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	(BND_REGNO_P): New.
	(ANY_BND_REG_P): New.
	(BNDmode): New.
	(HI_REGISTER_NAMES): Add bound registers.
	* config/i386/i386.md (UNSPEC_BNDMK): New.
	(UNSPEC_BNDMK_ADDR): New.
	(UNSPEC_BNDSTX): New.
	(UNSPEC_BNDLDX): New.
	(UNSPEC_BNDLDX_ADDR): New.
	(UNSPEC_BNDCL): New.
	(UNSPEC_BNDCU): New.
	(UNSPEC_BNDCN): New.
	(UNSPEC_MPX_FENCE): New.
	(BND0_REG): New.
	(BND1_REG): New.
	(type): Add mpxmov, mpxmk, mpxchk, mpxld, mpxst.
	(length_immediate): Likewise.
	(prefix_0f): Likewise.
	(memory): Likewise.
	(prefix_rep): Check for bnd prefix.
	(BND): New.
	(bnd_ptr): New.
	(BNDCHECK): New.
	(bndcheck): New.
	(*jcc_1): Add MPX bnd prefix and fix length.
	(*jcc_2): Likewise.
	(jump): Likewise.
	(simple_return_internal): Likewise.
	(simple_return_pop_internal): Likewise.
	(*indirect_jump): Add MPX bnd prefix.
	(*tablejump_1): Likewise.
	(simple_return_internal_long): Likewise.
	(simple_return_indirect_internal): Likewise.
	(<mode>_mk): New.
	(*<mode>_mk): New.
	(mov<mode>): New.
	(*mov<mode>_internal_mpx): New.
	(<mode>_<bndcheck>): New.
	(*<mode>_<bndcheck>): New.
	(<mode>_ldx): New.
	(*<mode>_ldx): New.
	(<mode>_stx): New.
	(*<mode>_stx): New.
	* config/i386/predicates.md (lea_address_operand): Rename to...
	(address_no_seg_operand): ... this.
	(address_mpx_no_base_operand): New.
	(address_mpx_no_index_operand): New.
	(bnd_mem_operator): New.
	* config/i386/i386.opt (mmpx): New.
	* doc/invoke.texi: Add documentation for the flags -mmpx, -mno-mpx.
	* doc/rtl.texi Add documentation for BND32mode and BND64mode.

Attachment: mpx-isa.patch
Description: Text document

Follow-Ups:
- Re: [PATCH, i386, MPX 1/X] Support of Intel MPX ISA. 2/2 New registers and instructions
  - From: Uros Bizjak

References:
- Re: [PATCH, i386, MPX 1/X] Support of Intel MPX ISA
  - From: Ilya Enkovich
- Re: [PATCH, i386, MPX 1/X] Support of Intel MPX ISA
  - From: Ilya Enkovich
- Re: [PATCH, i386, MPX 1/X] Support of Intel MPX ISA
  - From: Uros Bizjak
- Re: [PATCH, i386, MPX 1/X] Support of Intel MPX ISA
  - From: Ilya Enkovich
- Re: [PATCH, i386, MPX 1/X] Support of Intel MPX ISA
  - From: Uros Bizjak

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