RE: FW: [PATCH] [MIPS] microMIPS gcc support

["Moore, Catherine" <Catherine_Moore at mentor dot com>]

> -----Original Message-----
> From: Richard Sandiford [mailto:rdsandiford@googlemail.com]
> Sent: Thursday, March 21, 2013 8:04 PM
> To: Moore, Catherine
> Cc: gcc-patches@gcc.gnu.org; Rozycki, Maciej
> Subject: Re: FW: [PATCH] [MIPS] microMIPS gcc support
> 
> Thanks, this is almost there now.  It was only the problem with the new
> version of the move pattern (see below) that stopped this from being "OK
> with...".  The next round should be a formality though.
> 
Okay, modifications now made and patch attached.

> "Moore, Catherine" <Catherine_Moore@mentor.com> writes:
> > +(define_constraint "Uuw6"
> > +  "@internal
> > +   An unsigned constant of 6 bits."
> > +  (match_operand 0 "uw6_operand"))
> 
> ", shifted left two places".
> 
> > +	  (and (ior (eq_attr "compression" "micromips")
> > +		    (eq_attr "compression" "all"))
> 
> Please use (eq_attr "compression" "micromips,all") instead.
> 
> >  (define_insn "sub<mode>3"
> > -  [(set (match_operand:GPR 0 "register_operand" "=d")
> > -	(minus:GPR (match_operand:GPR 1 "register_operand" "d")
> > -		   (match_operand:GPR 2 "register_operand" "d")))]
> > +  [(set (match_operand:GPR 0 "register_operand" "=!u,d")
> > +	(minus:GPR (match_operand:GPR 1 "register_operand" "!u,d")
> > +		   (match_operand:GPR 2 "register_operand" "!u,d")))]
> >    ""
> > -  "<d>subu\t%0,%1,%2"
> > +  "@
> > +   <d>subu\t%0,%1,%2
> > +   <d>subu\t%0,%1,%2"
> 
> This change isn't needed.  It's OK (and IMO better) to keep a single asm string
> when the string is the same for all alternatives.
> 
> > @@ -4362,13 +4400,14 @@
> >  ;; in FP registers (off by default, use -mdebugh to enable).
> >
> >  (define_insn "*mov<mode>_internal"
> > -  [(set (match_operand:IMOVE32 0 "nonimmediate_operand"
> "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
> > -	(match_operand:IMOVE32 1 "move_operand"
> "d,Yd,Yf,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
> > +  [(set (match_operand:IMOVE32 0 "nonimmediate_operand"
> "=d,!u,d,e,!u,!u,!u,!u,!ks,d,ZS,ZV,ZU,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,
> *B*C*D,*d,*m")
> > +	(match_operand:IMOVE32 1 "move_operand"
> > +"d,J,Yd,Yf,Udb7,ZW,ZU,ZT,ZS,m,!ks,!u,!u,!u,dJ,*d*J,*m,*f,*f,*z,*d,*J*
> > +d,*a,*d,*m,*B*C*D,*B*C*D"))]
> 
> This pattern is only for 32-bit moves, so should only use ZS and ZT.
> (I don't mind keeping the definitions of the ZU...ZW constraints in this patch -
> - even though they start out unused -- because it's obvious they'll be needed
> eventually.  I'd prefer leaving the 8-bit and 16-move patterns themselves to a
> different patch though.)
> 
> Sorry, I should have noticed last time, but alternative 5 (u<-Udb7) should
> come before alternative 3 (d<-Yd), because d<-Yd includes everything that
> u<-Udb7 does.
> 
> > +extern bool m16_based_address_p (rtx, enum machine_mode, int
> > +(*)(rtx_def*, machine_mode));
> 
> Line too long: should be split after the first enum machine_mode.
> 
> Thanks,
> Richard

Attachment: short-delay-03-22.cl
Description: short-delay-03-22.cl

Attachment: short-delay-03-22.patch
Description: short-delay-03-22.patch