Trivial PA speedup

[Jeffrey A Law <law at cygnus dot com>]

I was analyzing some loop changes Joern & Bernd are working on and came
to the realization that reducing the dependency height for a single cycle
instruction probably isn't all that valuable, even on an out of order
execution machine :-)

And doing so does muck up a few loops by not creating indexed addressing
modes.

This patch removes the height reduction patterns for shadd.  Yahoo...

        * pa.md (shadd height reduction patterns/splitters): Remove.

Index: pa.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/pa/pa.md,v
retrieving revision 1.68
retrieving revision 1.69
diff -c -3 -p -r1.68 -r1.69
*** pa.md	2000/07/28 02:17:25	1.68
--- pa.md	2000/08/03 07:05:28	1.69
***************
*** 5166,5238 ****
    [(set_attr "type" "binary")
     (set_attr "length" "4")])
  
- ;; This anonymous pattern and splitter wins because it reduces the latency
- ;; of the shadd sequence without increasing the latency of the shift.
- ;;
- ;; We want to make sure and split up the operations for the scheduler since
- ;; these instructions can (and should) schedule independently.
- ;;
- ;; It would be clearer if combine used the same operator for both 
expressions,
- ;; it's somewhat confusing to have a mult in ine operation and an ashift
- ;; in the other.
- ;;
- ;; If this pattern is not split before register allocation, then we must 
expose
- ;; the fact that operand 4 is set before operands 1, 2 and 3 have been read.
- (define_insn ""
-   [(set (match_operand:SI 0 "register_operand" "=r")
- 	(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
- 			  (match_operand:SI 3 "shadd_operand" ""))
- 		 (match_operand:SI 1 "register_operand" "r")))
-    (set (match_operand:SI 4 "register_operand" "=&r")
- 	(ashift:SI (match_dup 2)
- 		   (match_operand:SI 5 "const_int_operand" "i")))]
-   "(INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))
-     && ! (reg_overlap_mentioned_p (operands[4], operands[2])))"
-   "#"
-   [(set_attr "type" "binary")
-    (set_attr "length" "8")])
- 
- (define_split
-   [(set (match_operand:SI 0 "register_operand" "=r")
- 	(plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
- 			  (match_operand:SI 3 "shadd_operand" ""))
- 		 (match_operand:SI 1 "register_operand" "r")))
-    (set (match_operand:SI 4 "register_operand" "=&r")
- 	(ashift:SI (match_dup 2)
- 		   (match_operand:SI 5 "const_int_operand" "i")))]
-   "INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
-   [(set (match_dup 4) (ashift:SI (match_dup 2) (match_dup 5)))
-    (set (match_dup 0) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
- 			       (match_dup 1)))]
-   "")
- 
- (define_insn ""
-   [(set (match_operand:DI 0 "register_operand" "=r")
- 	(plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
- 			  (match_operand:DI 3 "shadd_operand" ""))
- 		 (match_operand:DI 1 "register_operand" "r")))
-    (set (match_operand:DI 4 "register_operand" "=&r")
- 	(ashift:DI (match_dup 2)
- 		   (match_operand:DI 5 "const_int_operand" "i")))]
-   "TARGET_64BIT && INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
-   "#"
-   [(set_attr "type" "binary")
-    (set_attr "length" "8")])
- 
- (define_split
-   [(set (match_operand:DI 0 "register_operand" "=r")
- 	(plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
- 			  (match_operand:DI 3 "shadd_operand" ""))
- 		 (match_operand:DI 1 "register_operand" "r")))
-    (set (match_operand:DI 4 "register_operand" "=&r")
- 	(ashift:DI (match_dup 2)
- 		   (match_operand:DI 5 "const_int_operand" "i")))]
-   "TARGET_64BIT && INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
-   [(set (match_dup 4) (ashift:DI (match_dup 2) (match_dup 5)))
-    (set (match_dup 0) (plus:DI (mult:DI (match_dup 2) (match_dup 3))
- 			       (match_dup 1)))]
-   "")
- 
  (define_expand "ashlsi3"
    [(set (match_operand:SI 0 "register_operand" "")
  	(ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
--- 5166,5171 ----