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Re: Machine description for volatile memory access
- From: Segher Boessenkool <segher at kernel dot crashing dot org>
- To: William Tambe <tambewilliam at gmail dot com>
- Cc: gcc-help <gcc-help at gcc dot gnu dot org>
- Date: Mon, 9 Sep 2019 10:21:23 -0500
- Subject: Re: Machine description for volatile memory access
- References: <CAF8i9mNDK8K4v2t=7niqhgXEU-LfB-Dkm4En34YeFGJshn3PVw@mail.gmail.com>
On Mon, Sep 09, 2019 at 09:48:46AM -0500, William Tambe wrote:
> Does GCC support machine description for volatile memory accesses that
> must not be cached ?
> In other words, when using expressions such as theses, volatile memory
> access instructions should be use:
>
> volatile uint8_t *m;
> uint8_t n;
>
> *m = 5; // Should use a volatile memory store instruction.
> n = *m; // Should use a volatile memory load instruction.
>
> If GCC has support for the above, are there any examples I could be
> pointed to in the sources ?
There is no such thing as a "volatile memory load" (or store). What is
it you really want to do?
"volatile" is a concept in the C language. It doesn't translate to machine
instructions very well. You might want to use support for atomic (via
builtins for example), or write assembler (or inline asm).
Segher